SDMMCv1: fix system hang issues

1. SDMMCv1: unlock before waiting for DMA completion

Avoids system hanging forever when an error interrupt is signaled and
the controller is in a state where the DMA can never complete.

2. SDMMCv1: wait for DMA completion only when it will complete

In certain error states (e.g. CRC error in the middle of a multi-block
transmission), the DMA may never complete. Therefore, only wait for its
completion if the transfer was successful. We do need to wait for
completion on read as some words may still be in flight from the receive
FIFO to RAM.

The STM32F7 reference manual (RM0385 Rev 9 Section 35.3.2 SDMMC APB2
interface) mentions that it is possible for a receive FIFO overflow on
the last word to be signaled only after the DATAEND flag is set.
Therefore we also have to check that the FIFO does not have data in it
and confirm there is no RXOVERR error too.

3. SDMMCv1: listen for reserved start bit error

Sometimes this is the only interrupt that gets signaled in certain error
cases. We need to listen for it so we don't sleep forever waiting for an
interrupt from the controller.

The STM32F7 reference manual RM0385 documents this bit as reserved but
evidently it can still be triggered in some cases. The logic has been
copied from the SDIOv1 driver where it is not reserved.

Author: tpwrules

os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c

@@ -49,6 +49,19 @@
   STM32_DMA_GETCHANNEL(STM32_SDC_SDMMC2_DMA_STREAM,                         \
                        STM32_SDC_SDMMC2_DMA_CHN)
 
+/*
+ * Despite allegedly being reserved, the start bit error 9 was evidently
+ * inherited from SDIOv1 and will sometimes be asserted on error, so we need to
+ * detect it to avoid a forever wait for a transaction to complete.
+ */
+#if !defined(SDMMC_STA_STBITERR)
+#define SDMMC_STA_STBITERR      (0x1UL << 9U)
+#endif
+
+#if !defined(SDMMC_MASK_STBITERRIE)
+#define SDMMC_MASK_STBITERRIE   (0x1UL << 9U)
+#endif
+
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
@@ -171,6 +184,7 @@ static bool sdc_lld_prepare_read_bytes(SDCDriver *sdcp,
   sdcp->sdmmc->ICR   = SDMMC_ICR_ALL_FLAGS;
   sdcp->sdmmc->MASK  = SDMMC_MASK_DCRCFAILIE |
                        SDMMC_MASK_DTIMEOUTIE |
+                       SDMMC_MASK_STBITERRIE |
                        SDMMC_MASK_RXOVERRIE |
                        SDMMC_MASK_DATAENDIE;
   sdcp->sdmmc->DLEN  = bytes;
@@ -286,22 +300,31 @@ static bool sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n,
     osalThreadSuspendS(&sdcp->thread);
   }
 
-  /* Stopping operations, waiting for transfer completion at DMA level, then
-     the stream is disabled and cleared.*/
-  dmaWaitCompletion(sdcp->dma);
-  sdcp->sdmmc->MASK  = 0U;
-  sdcp->sdmmc->DCTRL = 0U;
+  /* Mask has now been set to zero by interrupt handler. */
+  osalSysUnlock();
 
+  /* Data transfer not complete, let error cleanup stop DMA.*/
   if ((sdcp->sdmmc->STA & SDMMC_STA_DATAEND) == 0U) {
-    osalSysUnlock();
     return HAL_FAILED;
   }
 
+  /* RXOVERR may be late, wait for RX FIFO to not have data (or be disabled).*/
+  while ((sdcp->sdmmc->STA & SDMMC_STA_RXDAVL) != 0U)
+    ;
+
+  /* RX data overflow, let error cleanup stop DMA.*/
+  if ((sdcp->sdmmc->STA & SDMMC_STA_RXOVERR) != 0U) {
+    return HAL_FAILED;
+  }
+
+  /* Waiting for transfer completion at DMA level, then the stream is disabled
+   and cleared.*/
+  dmaWaitCompletion(sdcp->dma);
+  sdcp->sdmmc->DCTRL = 0U;
+
   /* Clearing status.*/
   sdcp->sdmmc->ICR = SDMMC_ICR_ALL_FLAGS;
 
-  osalSysUnlock();
-
   /* Finalize transaction.*/
   if (n > 1U)
     return sdc_lld_send_cmd_short_crc(sdcp, MMCSD_CMD_STOP_TRANSMISSION, 0, resp);
@@ -332,8 +355,8 @@ static void sdc_lld_collect_errors(SDCDriver *sdcp, uint32_t sta) {
     errors |= SDC_TX_UNDERRUN;
   if (sta & SDMMC_STA_RXOVERR)
     errors |= SDC_RX_OVERRUN;
-/*  if (sta & SDMMC_STA_STBITERR)
-    errors |= SDC_STARTBIT_ERROR;*/
+  if (sta & SDMMC_STA_STBITERR)
+    errors |= SDC_STARTBIT_ERROR;
 
   sdcp->errors |= errors;
 }
@@ -859,6 +882,7 @@ bool sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
   sdcp->sdmmc->ICR   = SDMMC_ICR_ALL_FLAGS;
   sdcp->sdmmc->MASK  = SDMMC_MASK_DCRCFAILIE |
                        SDMMC_MASK_DTIMEOUTIE |
+                       SDMMC_MASK_STBITERRIE |
                        SDMMC_MASK_RXOVERRIE |
                        SDMMC_MASK_DATAENDIE;
   sdcp->sdmmc->DLEN  = blocks * MMCSD_BLOCK_SIZE;
@@ -927,6 +951,7 @@ bool sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk,
   sdcp->sdmmc->ICR   = SDMMC_ICR_ALL_FLAGS;
   sdcp->sdmmc->MASK  = SDMMC_MASK_DCRCFAILIE |
                        SDMMC_MASK_DTIMEOUTIE |
+                       SDMMC_MASK_STBITERRIE |
                        SDMMC_MASK_TXUNDERRIE |
                        SDMMC_MASK_DATAENDIE;
   sdcp->sdmmc->DLEN  = blocks * MMCSD_BLOCK_SIZE;