1+ --------------------------------------------------------------------------------
2+ --
3+ -- CTU CAN FD IP Core
4+ -- Copyright (C) 2021-present Ondrej Ille
5+ --
6+ -- Permission is hereby granted, free of charge, to any person obtaining a copy
7+ -- of this VHDL component and associated documentation files (the "Component"),
8+ -- to use, copy, modify, merge, publish, distribute the Component for
9+ -- educational, research, evaluation, self-interest purposes. Using the
10+ -- Component for commercial purposes is forbidden unless previously agreed with
11+ -- Copyright holder.
12+ --
13+ -- The above copyright notice and this permission notice shall be included in
14+ -- all copies or substantial portions of the Component.
15+ --
16+ -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17+ -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18+ -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19+ -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20+ -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21+ -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
22+ -- IN THE COMPONENT.
23+ --
24+ -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
25+ -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
26+ -- protocol license from Bosch.
27+ --
28+ -- -------------------------------------------------------------------------------
29+ --
30+ -- CTU CAN FD IP Core
31+ -- Copyright (C) 2015-2020 MIT License
32+ --
33+ -- Authors:
34+ -- Ondrej Ille <ondrej.ille@gmail.com>
35+ -- Martin Jerabek <martin.jerabek01@gmail.com>
36+ --
37+ -- Project advisors:
38+ -- Jiri Novak <jnovak@fel.cvut.cz>
39+ -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
40+ --
41+ -- Department of Measurement (http://meas.fel.cvut.cz/)
42+ -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
43+ -- Czech Technical University (http://www.cvut.cz/)
44+ --
45+ -- Permission is hereby granted, free of charge, to any person obtaining a copy
46+ -- of this VHDL component and associated documentation files (the "Component"),
47+ -- to deal in the Component without restriction, including without limitation
48+ -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
49+ -- and/or sell copies of the Component, and to permit persons to whom the
50+ -- Component is furnished to do so, subject to the following conditions:
51+ --
52+ -- The above copyright notice and this permission notice shall be included in
53+ -- all copies or substantial portions of the Component.
54+ --
55+ -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
56+ -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
57+ -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
58+ -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
59+ -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
60+ -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
61+ -- IN THE COMPONENT.
62+ --
63+ -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
64+ -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
65+ -- protocol license from Bosch.
66+ --
67+ --------------------------------------------------------------------------------
68+
69+ --------------------------------------------------------------------------------
70+ -- @TestInfoStart
71+ --
72+ -- @Purpose:
73+ -- Self acknowledge mode test
74+ --
75+ -- @Verifies:
76+ -- @1. When MODE[SAM] = 1 and CTU CAN FD transmits a frame, then it will
77+ -- send dominant ACK bit.
78+ --
79+ -- @Test sequence:
80+ -- @1. Configure Self acknowledge mode in DUT Node.
81+ -- @2. Send frame by DUT. Wait till ACK field in DUT Node.
82+ -- @3. Check that DUT Node is transmitting Dominant value. Wait until bus
83+ -- is idle.
84+ --
85+ -- @TestInfoEnd
86+ --------------------------------------------------------------------------------
87+ -- Revision History:
88+ -- 8.9.2024 Created file
89+ --------------------------------------------------------------------------------
90+
91+ Library ctu_can_fd_tb;
92+ context ctu_can_fd_tb.ieee_context;
93+ context ctu_can_fd_tb.rtl_context;
94+ context ctu_can_fd_tb.tb_common_context;
95+
96+ use ctu_can_fd_tb.feature_test_agent_pkg.all ;
97+
98+ package mode_self_acknowledge_ftest is
99+ procedure mode_self_acknowledge_ftest_exec(
100+ signal chn : inout t_com_channel
101+ );
102+ end package ;
103+
104+
105+ package body mode_self_acknowledge_ftest is
106+ procedure mode_self_acknowledge_ftest_exec(
107+ signal chn : inout t_com_channel
108+ ) is
109+ variable CAN_TX_frame : SW_CAN_frame_type;
110+ variable CAN_RX_frame : SW_CAN_frame_type;
111+ variable frame_sent : boolean := false ;
112+ variable mode_1 : SW_mode := SW_mode_rst_val;
113+ variable mode_2 : SW_mode := SW_mode_rst_val;
114+
115+ variable txt_buf_state : SW_TXT_Buffer_state_type;
116+ variable rx_buf_state : SW_RX_Buffer_info;
117+ variable status : SW_status;
118+ variable frames_equal : boolean := false ;
119+ variable pc_dbg : SW_PC_Debug;
120+
121+ variable can_tx : std_logic ;
122+ begin
123+
124+ ------------------------------------------------------------------------
125+ -- @1. Configures Self Acknowledge mode in DUT.
126+ ------------------------------------------------------------------------
127+ info_m(" Step 1"
128+
129+ mode_1.self_acknowledge := true ;
130+ set_core_mode(mode_1, DUT_NODE, chn);
131+
132+ ------------------------------------------------------------------------
133+ -- @2. Send frame by DUT. Wait till ACK field in DUT Node.
134+ ------------------------------------------------------------------------
135+ info_m(" Step 2"
136+
137+ CAN_generate_frame(CAN_TX_frame);
138+ CAN_send_frame(CAN_TX_frame, 1 , DUT_NODE, chn, frame_sent);
139+ CAN_wait_pc_state(pc_deb_ack, DUT_NODE, chn);
140+ CAN_wait_sync_seg(DUT_NODE, chn);
141+ wait for 20 ns ;
142+
143+ ------------------------------------------------------------------------
144+ -- @3. Check that DUT Node is transmitting Dominant value.
145+ -- Wait until bus is idle.
146+ ------------------------------------------------------------------------
147+ info_m(" Step 3"
148+
149+ get_can_tx(DUT_NODE, can_tx, chn);
150+ check_m(can_tx = DOMINANT, " DUT transmits dominant ACK when MODE[SAM]=1"
151+ CAN_wait_bus_idle(DUT_NODE, chn);
152+
153+ end procedure ;
154+
155+ end package body ;
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