design: per-writer reclock lanes, table-bound reclock, data-domain compaction as a reduce

Folds in the review (and the CHANGES carrier-naming we converged on):
- CHANGES/INTEGRATE are symmetric on named carriers: CHANGES(rel, TIME=>, DIFF=>)
  produces them, INTEGRATE(rel, TIME=>, DIFF=>) consumes them; bare CHANGES(rel)
  exposes none. No reserved/implicit columns.
- Drop the per-operator RECLOCK argument. The reclock is bound 1:1 to the table
  (inferred from rel's lineage); a per-site reclock could let two INTEGRATEs of one
  table disagree. Recorded as a rejected alternative.
- One reclock per table, structurally and necessarily (B is one shard/one clock);
  all RECORDs and all INTEGRATEs of a table share it, so multiple INTEGRATEs are
  consistent by construction. The table is the unit of shared completeness.
- Multi-writer via per-writer reclock lanes R_i: B -> X_i with a read-time meet
  (no merged frontier, no inter-writer coordination); add = register lane >= upper,
  drop = lane leaves the meet (one-way), drop-all = table seals (finalization).
- Data-domain compaction promoted to the named primitive and made precise: a reduce
  (clamp change_ts := max(change_ts, t) then GROUP BY <data cols, clamped ts>,
  SUM(change_diff)), NOT a bare in-place clamp (identical clamped SourceData merges
  to persist mult 2 while the data column reads +1 — a consequence of diff-as-data).
  Reclock-free, recorder-free, idempotent/monotone; A-since distinct from B-since.
- Propagated through both docs (surface, reclock decision, multi-writer, bounding,
  alternatives, open questions; impl change-map/M3/M4/phases/Q7).

https://claude.ai/code/session_015YFH7J7PaEqkBSrAQYaq8H

Author: claude