This is a simple test for Fletchgen to read strings from an Arrow Recordbatch in simulation.
The files in this folder contain the following:
test.vhd : Accelerator implementation test.fbs : Schema Flatbuffer file test.rb : A RecordBatch based on the schema with some strings (human names)
Running fletchgen with:
fletchgen \
-i test.fbs \
-o test_wrapper.vhd \
-n test \
-w test_wrapper \
-s test.fbs \
-d test.rb \
--sim sim_top.vhd \
-x test.srecWill produce:
test_wrapper.vhd : Generated wrapper sim_top.vhd : Simulation (testbench) top-level test.srec : An SREC file for the memory model in simulation.
Now, sim_top.vhd can be simulated. There is a TCL script for QuestaSim:
vsim -do stringread.tclAfter expanding the UserCore wave group in the wave window, you can change the radix of the output data to ASCII and observe the names being streamed into the accelerator core. To change the radix you may issue the TCL command:
property wave -radix ASCII *chars_out_dataIn this test, the elements per cycle is set to 4, so we will see the first four characters from right to left, A, l, i and c, on the output:
