1+ # Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved.
2+ #
3+ # Licensed under the Apache License, Version 2.0 (the "License");
4+ # you may not use this file except in compliance with the License.
5+ # You may obtain a copy of the License at
6+ #
7+ # http://www.apache.org/licenses/LICENSE-2.0
8+ #
9+ # Unless required by applicable law or agreed to in writing, software
10+ # distributed under the License is distributed on an "AS IS" BASIS,
11+ # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12+ # See the License for the specific language governing permissions and
13+ # limitations under the License.
14+ """GB200 performance recipes for Llama 2."""
15+
16+ from megatron .bridge .perf_recipes .environment import COMMON_PERF_ENV_VARS
17+ from megatron .bridge .perf_recipes .llama .common import (
18+ CommOverlapConfig ,
19+ ConfigContainer ,
20+ _llama2_benchmark_common ,
21+ _llama2_70b_precision_config ,
22+ llama2_70b_peft_config ,
23+ )
24+
25+ def llama2_70b_peft_4gpu_gb200_fp8ds_config () -> ConfigContainer :
26+ """Llama 2 70B LoRA: 4× GB200, FP8 DS, GBS=8, seq_length=2048."""
27+ cfg = llama2_70b_peft_config (peft_scheme = "lora" )
28+ cfg .mixed_precision = _llama2_70b_precision_config ("fp8_ds" )
29+ _llama2_benchmark_common (cfg )
30+
31+ cfg .model .tensor_model_parallel_size = 1
32+ cfg .model .pipeline_model_parallel_size = 1
33+ cfg .model .context_parallel_size = 1
34+ cfg .train .global_batch_size = 8
35+ cfg .train .micro_batch_size = 1
36+ cfg .model .cuda_graph_impl = None
37+ cfg .model .cuda_graph_scope = None
38+ cfg .model .cpu_offloading_num_layers = 20
39+ cfg .model .cpu_offloading = True
40+ cfg .validation .eval_global_batch_size = 4
41+ cfg .validation .eval_interval = 48
42+ cfg .validation .eval_iters = 44
43+ cfg .validation .start_at_eval_iter = 192
44+ cfg .scheduler .lr_decay_iters = 800
45+ cfg .scheduler .lr_decay_steps = 6400
46+ cfg .scheduler .wd_incr_steps = 6400
47+ cfg .dataset .max_train_samples = 6432
48+ cfg .dataset .num_workers = 4
49+ cfg .dataset .seed = 30339
50+ cfg .rng .seed = 30339
51+ # Keep process settings next to the recipe so users can see the exact benchmark environment.
52+ cfg .env_vars = {
53+ ** COMMON_PERF_ENV_VARS ,
54+ # CUDA stream scheduling for this model and parallel layout.
55+ "CUDA_DEVICE_MAX_CONNECTIONS" : 1 ,
56+ # CUDA graph and allocator behavior for this recipe.
57+ "NCCL_GRAPH_REGISTER" : 0 ,
58+ "PYTORCH_CUDA_ALLOC_CONF" : "expandable_segments:True" ,
59+ "TORCH_NCCL_AVOID_RECORD_STREAMS" : 1 ,
60+ # NCCL user-buffer and launch settings.
61+ "NCCL_NVLS_ENABLE" : 1 ,
62+ # Transformer Engine overlap settings for this model.
63+ "NVTE_BWD_LAYERNORM_SM_MARGIN" : 20 ,
64+ "NVTE_FWD_LAYERNORM_SM_MARGIN" : 20 ,
65+ }
66+ return cfg
67+
68+
69+ def llama2_70b_peft_8gpu_gb200_fp8ds_config () -> ConfigContainer :
70+ """Llama 2 70B LoRA: 8× GB200, FP8 DS, GBS=8, seq_length=2048."""
71+ cfg = llama2_70b_peft_config (peft_scheme = "lora" )
72+ cfg .mixed_precision = _llama2_70b_precision_config ("fp8_ds" )
73+ _llama2_benchmark_common (cfg )
74+
75+ cfg .model .tensor_model_parallel_size = 1
76+ cfg .model .pipeline_model_parallel_size = 1
77+ cfg .model .context_parallel_size = 1
78+ cfg .train .global_batch_size = 8
79+ cfg .train .micro_batch_size = 1
80+ cfg .model .cuda_graph_impl = "local"
81+ cfg .model .cuda_graph_scope = "full_iteration"
82+ cfg .model .cpu_offloading_num_layers = 11
83+ cfg .model .cpu_offloading = True
84+ cfg .validation .eval_global_batch_size = 8
85+ cfg .validation .eval_interval = 48
86+ cfg .validation .eval_iters = 22
87+ cfg .validation .start_at_eval_iter = 192
88+ cfg .scheduler .lr_decay_iters = 800
89+ cfg .scheduler .lr_decay_steps = 6400
90+ cfg .scheduler .wd_incr_steps = 6400
91+ cfg .dataset .max_train_samples = 6432
92+ cfg .dataset .num_workers = 4
93+ cfg .dataset .seed = 27208
94+ cfg .rng .seed = 27208
95+ # Keep process settings next to the recipe so users can see the exact benchmark environment.
96+ cfg .env_vars = {
97+ ** COMMON_PERF_ENV_VARS ,
98+ # CUDA stream scheduling for this model and parallel layout.
99+ "CUDA_DEVICE_MAX_CONNECTIONS" : 1 ,
100+ # CUDA graph and allocator behavior for this recipe.
101+ "NCCL_GRAPH_REGISTER" : 0 ,
102+ "PYTORCH_CUDA_ALLOC_CONF" : "expandable_segments:True" ,
103+ "TORCH_NCCL_AVOID_RECORD_STREAMS" : 1 ,
104+ # NCCL user-buffer and launch settings.
105+ "NCCL_NVLS_ENABLE" : 1 ,
106+ # Transformer Engine overlap settings for this model.
107+ "NVTE_BWD_LAYERNORM_SM_MARGIN" : 20 ,
108+ "NVTE_FWD_LAYERNORM_SM_MARGIN" : 20 ,
109+ }
110+ return cfg
111+
112+
113+ def llama2_70b_peft_8gpu_gb200_nvfp4_config () -> ConfigContainer :
114+ """Llama 2 70B LoRA: 8× GB200, NVFP4, GBS=8, seq_length=2048."""
115+ cfg = llama2_70b_peft_config (peft_scheme = "lora" )
116+ cfg .mixed_precision = _llama2_70b_precision_config ("nvfp4" )
117+ _llama2_benchmark_common (cfg )
118+
119+ cfg .model .tensor_model_parallel_size = 1
120+ cfg .model .pipeline_model_parallel_size = 1
121+ cfg .model .context_parallel_size = 2
122+ cfg .train .global_batch_size = 8
123+ cfg .train .micro_batch_size = 1
124+ cfg .model .cuda_graph_impl = "local"
125+ cfg .model .cuda_graph_scope = "full_iteration"
126+ cfg .model .cpu_offloading_num_layers = 20
127+ cfg .optimizer .lr = 0.0006
128+ cfg .validation .eval_global_batch_size = 4
129+ cfg .validation .eval_interval = 48
130+ cfg .validation .eval_iters = 44
131+ cfg .validation .start_at_eval_iter = 192
132+ cfg .scheduler .lr_decay_iters = 700
133+ cfg .scheduler .lr_decay_steps = 5600
134+ cfg .scheduler .wd_incr_steps = 5600
135+ cfg .dataset .max_train_samples = 5628
136+ cfg .dataset .num_workers = 4
137+ cfg .dataset .seed = 23829
138+ cfg .rng .seed = 23829
139+ # Keep process settings next to the recipe so users can see the exact benchmark environment.
140+ cfg .env_vars = {
141+ ** COMMON_PERF_ENV_VARS ,
142+ # CUDA stream scheduling for this model and parallel layout.
143+ "CUDA_DEVICE_MAX_CONNECTIONS" : 1 ,
144+ # CUDA graph and allocator behavior for this recipe.
145+ "NCCL_GRAPH_REGISTER" : 0 ,
146+ "PYTORCH_CUDA_ALLOC_CONF" : "expandable_segments:True" ,
147+ "TORCH_NCCL_AVOID_RECORD_STREAMS" : 1 ,
148+ # NCCL user-buffer and launch settings.
149+ "NCCL_NVLS_ENABLE" : 1 ,
150+ # Transformer Engine overlap settings for this model.
151+ "NVTE_BWD_LAYERNORM_SM_MARGIN" : 20 ,
152+ "NVTE_FWD_LAYERNORM_SM_MARGIN" : 20 ,
153+ }
154+ return cfg
155+
156+
157+ def llama2_70b_peft_72gpu_gb200_fp8ds_config () -> ConfigContainer :
158+ """Llama 2 70B LoRA: 72× GB200, FP8 DS, GBS=8, seq_length=2048."""
159+ cfg = llama2_70b_peft_config (peft_scheme = "lora" )
160+ cfg .mixed_precision = _llama2_70b_precision_config ("fp8_ds" )
161+ _llama2_benchmark_common (cfg )
162+
163+ cfg .model .tensor_model_parallel_size = 1
164+ cfg .model .pipeline_model_parallel_size = 1
165+ cfg .model .context_parallel_size = 8
166+ cfg .train .global_batch_size = 9
167+ cfg .train .micro_batch_size = 1
168+ cfg .model .cuda_graph_impl = "local"
169+ cfg .model .cuda_graph_scope = "full_iteration"
170+ cfg .model .cpu_offloading_num_layers = 20
171+ cfg .model .cpu_offloading = True
172+ cfg .validation .eval_global_batch_size = 8
173+ cfg .validation .eval_global_batch_size = 36
174+ cfg .validation .eval_interval = 43
175+ cfg .validation .eval_iters = 5
176+ cfg .validation .start_at_eval_iter = 172
177+ cfg .scheduler .lr_decay_iters = 800
178+ cfg .scheduler .lr_decay_steps = 7200
179+ cfg .scheduler .wd_incr_steps = 7200
180+ cfg .dataset .max_train_samples = 7236
181+ cfg .dataset .num_workers = 2
182+ cfg .dataset .seed = 16584
183+ cfg .rng .seed = 16584
184+ # Keep process settings next to the recipe so users can see the exact benchmark environment.
185+ cfg .env_vars = {
186+ ** COMMON_PERF_ENV_VARS ,
187+ # CUDA stream scheduling for this model and parallel layout.
188+ "CUDA_DEVICE_MAX_CONNECTIONS" : 1 ,
189+ # CUDA graph and allocator behavior for this recipe.
190+ "NCCL_GRAPH_REGISTER" : 0 ,
191+ "PYTORCH_CUDA_ALLOC_CONF" : "expandable_segments:True" ,
192+ "TORCH_NCCL_AVOID_RECORD_STREAMS" : 1 ,
193+ # NCCL user-buffer and launch settings.
194+ "NCCL_NVLS_ENABLE" : 1 ,
195+ # Transformer Engine overlap settings for this model.
196+ "NVTE_BWD_LAYERNORM_SM_MARGIN" : 20 ,
197+ "NVTE_FWD_LAYERNORM_SM_MARGIN" : 20 ,
198+ }
199+ return cfg
200+
201+
202+ def llama2_70b_peft_512gpu_gb200_fp8ds_config () -> ConfigContainer :
203+ """Llama 2 70B LoRA: 512× GB200, FP8 DS, GBS=8, seq_length=2048."""
204+ cfg = llama2_70b_peft_config (peft_scheme = "lora" )
205+ cfg .mixed_precision = _llama2_70b_precision_config ("fp8_ds" )
206+ _llama2_benchmark_common (cfg )
207+
208+ cfg .model .tensor_model_parallel_size = 1
209+ cfg .model .pipeline_model_parallel_size = 1
210+ cfg .model .context_parallel_size = 8
211+ cfg .train .global_batch_size = 64
212+ cfg .train .micro_batch_size = 1
213+ cfg .model .cuda_graph_impl = "local"
214+ cfg .model .cuda_graph_scope = "full_iteration"
215+ cfg .model .cpu_offloading_num_layers = 20
216+ cfg .model .cpu_offloading = True
217+ cfg .optimizer .lr = 0.0006
218+ cfg .validation .eval_global_batch_size = 64
219+ cfg .validation .eval_interval = 6
220+ cfg .validation .eval_iters = 3
221+ cfg .validation .start_at_eval_iter = 66
222+ cfg .scheduler .lr_decay_iters = 600
223+ cfg .scheduler .lr_decay_steps = 38400
224+ cfg .scheduler .wd_incr_steps = 38400
225+ cfg .dataset .max_train_samples = 38592
226+ cfg .dataset .num_workers = 2
227+ cfg .dataset .seed = 22205
228+ cfg .rng .seed = 22205
229+ # Keep process settings next to the recipe so users can see the exact benchmark environment.
230+ cfg .env_vars = {
231+ ** COMMON_PERF_ENV_VARS ,
232+ # CUDA stream scheduling for this model and parallel layout.
233+ "CUDA_DEVICE_MAX_CONNECTIONS" : 1 ,
234+ # CUDA graph and allocator behavior for this recipe.
235+ "NCCL_GRAPH_REGISTER" : 0 ,
236+ "PYTORCH_CUDA_ALLOC_CONF" : "expandable_segments:True" ,
237+ "TORCH_NCCL_AVOID_RECORD_STREAMS" : 1 ,
238+ # NCCL user-buffer and launch settings.
239+ "NCCL_NVLS_ENABLE" : 1 ,
240+ # Transformer Engine overlap settings for this model.
241+ "NVTE_BWD_LAYERNORM_SM_MARGIN" : 20 ,
242+ "NVTE_FWD_LAYERNORM_SM_MARGIN" : 20 ,
243+ }
244+ return cfg
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