samples: sync ntt-fpga history

Author: grandchildrice

examples/ntt-fpga/evidence/index.json

@@ -0,0 +1,75 @@
+{
+  "id": "ntt-fpga",
+  "fetchedAt": "2026-06-19T08:12:32.064Z",
+  "sources": [
+    {
+      "title": "CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture (TCHES 2022)",
+      "url": "https://tches.iacr.org/index.php/TCHES/article/view/9291"
+    },
+    {
+      "title": "CFNTT PDF (IACR TCHES)",
+      "url": "https://tches.iacr.org/index.php/TCHES/article/download/9291/8857"
+    },
+    {
+      "title": "DOI 10.46586/tches.v2022.i1.94-126",
+      "url": "https://doi.org/10.46586/tches.v2022.i1.94-126"
+    },
+    {
+      "url": "https://tches.iacr.org/index.php/TCHES/article/view/9291"
+    }
+  ],
+  "items": [
+    {
+      "kind": "paper",
+      "file": "paper.md"
+    }
+  ],
+  "attempts": [
+    {
+      "method": "paper",
+      "at": "2026-06-19T07:46:21.997Z",
+      "gaps": [
+        "[operation] Exact conflict-free bank-index and offset functions, and the per-stage crossbar permutation table σ_s (the paper's headline Sec. III result) (part crossbar_network)",
+        "[shape] BRAM depth is inconsistent: bram_0 declares depth_words=256 but the crossbar/offset map uses 128 words/bank (part bram_0)",
+        "[operation] Twiddle-ROM addressing f(stage,block) under the rearranged-loop twiddle-reuse structure (only a seed power table + generator are given) (part twiddle_rom)",
+        "[control] Full radix-4 transform schedule: the fused two-stage pass and radix-4 conflict-free addressing (only the butterfly unit is pinned) (part config_radix_selector)",
+        "[timing] Radix-4 cycle accounting: reconcile bf_cycles_per_stage_r4=32 / total=160 against 256 BUs / 4 lanes = 64 cycles/stage (part config_radix_selector)",
+        "[param] Radix-4 butterfly multiplier count contradiction (3 mults in config_radix_selector vs 2 mults in op-count reconciliation) (part config_radix_selector)",
+        "[control] Exact FSM transition table (spec lists states but calls the transitions reconstructed/unpublished) (part schedule_controller)",
+        "[port] PCIe/DMA framing, handshake and beat packing at the host boundary (recorded as reproduction-invented) (part host_phy)",
+        "[param] Paper's true modulus (source gives only '14-bit NTT-friendly prime'; q=12289 is a reproduction fix)",
+        "parameter \"radix\" — the source's real value (impls guessed \"2 implemented; 4 only as a butterfly unit, not full schedule\")",
+        "evidence for the named property \"Conflict-free memory mapping (arbitrary radix/#BU, no bank conflict)\"",
+        "evidence for the named property \"No bit-reversal stage / natural-order output\"",
+        "evidence for the named property \"Radix-4: 33% fewer mults / 20% fewer add/sub\"",
+        "evidence for the named property \"~50% butterfly hardware saved via symmetric operators\"",
+        "evidence for the named property \"ATP advantage 2.2x/1.2x/1.1x/1.9x LUT/FF/DSP/BRAM vs radix-2\"",
+        "the source's actual structure for: The paper's defining feature — the conflict-free interleaved-bank mapping and per-stage crossbar permutation — is replaced by a reproduction-chosen XOR-fold in both impls; the actual routing topology is unverified."
+      ],
+      "bytes": 10283
+    },
+    {
+      "method": "refs",
+      "at": "2026-06-19T08:12:32.064Z",
+      "gaps": [
+        "[operation] Paper's actual conflict-free (bank,offset) mapping function and per-stage crossbar permutation sigma_s (the headline Sec. III contribution)",
+        "[operation] Twiddle-ROM addressing function f(stage,block) under the rearranged twiddle-reuse loop",
+        "[control] Exact FSM transition table and per-state cycle latencies (only aggregate 9 cycles/lane given)",
+        "[param] Naive-radix-4 add/sub baseline (10 assumed) that pins the 20% reduction claim",
+        "[operation] Whether output is genuinely bit-reversal-free in hardware vs. computed bit-reversed then relabeled",
+        "[param] Specific 14-bit modulus of the paper benchmark (q=12289 is a reproduction fix, not the stated prime)",
+        "[port] Host PCIe/DMA framing, beat packing and handshake (explicitly reproduction-invented) (part pcb_substrate)",
+        "evidence for the named property \"Conflict-free memory mapping (arbitrary radix/#BU, no bank conflict)\"",
+        "evidence for the named property \"No bit-reversal stage / natural-order output\"",
+        "evidence for the named property \"Twiddle-factor reuse via rearranged loop\"",
+        "evidence for the named property \"radix-4 uses 33% fewer mults / 20% fewer add/sub (vs NAIVE radix-4)\"",
+        "evidence for the named property \"~50% butterfly hardware saved via symmetric operators\"",
+        "evidence for the named property \"ATP LUT/FF/DSP/BRAM ~2.2x/1.2x/1.1x/1.9x lower than radix-2\"",
+        "the source's actual structure for: The architecture's headline contribution — the conflict-free interleaved-BRAM mapping and crossbar permutation — is replaced by a guessed XOR-fold in both impls; the SPECIFIC mapping the paper describes is not reproduced",
+        "the source's actual structure for: Twiddle addressing uses generic bit-reversed ROM layout rather than the paper's rearranged twiddle-reuse loop, so the memory-footprint/reuse optimization is structurally absent",
+        "the source's actual structure for: Functional Python models do not realize the 9-cycle pipeline (mult 3 + add/sub 1 + Barrett 4 + reg 1) as actual pipeline stages — latency is only asserted as a bound"
+      ],
+      "bytes": 17665
+    }
+  ]
+}