Commit 25170b5
fix(cllc): converge steady-state at the resonant load-independent point
The CLLC frontend scenario (400 V in, 400 V / 8.25 A out, fr = fsw = 120 kHz,
n = 1, symmetric tank) printed "[CLLC] steady-state solver did not fully
converge" (~2.44 A residual), which the frontend treats as an error — even
though the emitted waveform already matches SPICE (the reference-design PtP
tests pass). Two issues, both fixed:
- Observable residual. The convergence residual was the 4-state antisymmetry
norm over {iLr1, iLm, vCr1, vCr2}. The two series resonant caps are tracked
independently, but the tank only ever sees their SUM (Vc = vCr1 + vCr2); the
common-mode split between them is a gauge freedom that affects no waveform.
The raw norm penalized that unobservable split (and mixed amps with volts),
reading ~2.4 at the load-independent point while the physical state was
converged. Gate and report on the antisymmetry of the OBSERVABLE states only:
iLr1, iLm, and the total cap voltage (vCr1 + vCr2).
- LIP perturbation removed on this path. The 0.5% Vi perturbation existed only
to keep a Newton Jacobian non-singular at Vi ≈ Vo, but the 4-state path uses
damped Picard (no Jacobian). It only injected a ~0.5% inconsistency between
the solved seed (Vi·1.005) and the re-propagated waveform (true Vi), which
surfaced directly as residual. Solving at the true Vi makes the converged
state self-consistent.
Result: residual 2.44 -> below the 0.5 gate. [cllc-topology] 36/36 pass and
CLLC reference-design PtP 6/6 pass (waveforms unchanged within SPICE agreement).
Test: Test_Cllc_FrontendRepro_SteadyState_Converges (TestCllc.cpp).
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>1 parent d941a27 commit 25170b5
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