Skip to content

Commit fa574eb

Browse files
authored
CANpiler: Jinja Decouple Filter Gen Logic (#262)
1 parent b991d60 commit fa574eb

File tree

8 files changed

+104
-86
lines changed

8 files changed

+104
-86
lines changed

.vscode/tasks.json

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -11,17 +11,17 @@
1111
}
1212
},
1313
{
14-
"label": "build_bl",
14+
"label": "build with fanalyzer",
1515
"type": "shell",
16-
"command": "python3 per_build.py --bootloader",
16+
"command": "python3 per_build.py --fanalyzer",
1717
"group": {
1818
"kind": "build"
1919
}
2020
},
2121
{
22-
"label": "build_fanalyzer",
22+
"label": "build with bootloader",
2323
"type": "shell",
24-
"command": "python3 per_build.py --fanalyzer",
24+
"command": "python3 per_build.py --bootloader",
2525
"group": {
2626
"kind": "build"
2727
}
@@ -35,13 +35,15 @@
3535
}
3636
},
3737
{
38-
"label": "canlib_gen",
38+
"label": "generate can library",
3939
"type": "shell",
4040
"command": "python3 ./common/can_library/canpiler/build.py",
41-
"problemMatcher": []
41+
"group": {
42+
"kind": "build"
43+
}
4244
},
4345
{
44-
"label": "docs_gen",
46+
"label": "run doxygen",
4547
"type": "shell",
4648
"command": "doxygen Doxyfile"
4749
}

common/can_library/canpiler/templates/bus_header.h.jinja

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,4 +29,4 @@ typedef struct {
2929
} {{ msg.name }}_data_t;
3030

3131
{% endfor %}
32-
#endif
32+
#endif // {{ bus_name|upper }}_H
Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
// bxCAN filter setup for {{ periph }}
2+
static inline void {{ periph }}_set_filters() {
3+
{% set banks = mapping.filters.get(periph, []) %}
4+
{% set accept_all = mapping.accept_all.get(periph, False) %}
5+
{% if not banks and not accept_all %}
6+
return;
7+
{% elif accept_all %}
8+
// Accept all messages
9+
{% set bank_idx = 0 if periph == "CAN1" else 14 %}
10+
{{ periph }}->FM1R &= ~(1 << {{ bank_idx }}); // Mask mode
11+
{{ periph }}->FS1R |= (1 << {{ bank_idx }}); // 32-bit scale
12+
{{ periph }}->FA1R |= (1 << {{ bank_idx }});
13+
{{ periph }}->sFilterRegister[{{ bank_idx }}].FR1 = 0;
14+
{{ periph }}->sFilterRegister[{{ bank_idx }}].FR2 = 0;
15+
{% else %}
16+
{{ periph }}->FM1R |= 0x07FFFFFF; // Set banks 0-27 to id mode
17+
{{ periph }}->FS1R |= 0x07FFFFFF; // Set banks 0-27 to 32-bit scale
18+
19+
{% for fb in banks %}
20+
// Bank {{ fb.bank_idx }}: {{ fb.msg1.name }}{% if fb.msg2 %}, {{ fb.msg2.name }}{% endif %}
21+
22+
{{ periph }}->FA1R |= (1 << {{ fb.bank_idx }});
23+
{% set m1_macro = fb.msg1.macro_name ~ "_MSG_ID" %}
24+
{% if fb.is_ext1 %}
25+
{{ periph }}->sFilterRegister[{{ fb.bank_idx }}].FR1 = (({{ m1_macro }}) << 3) | 4;
26+
{% else %}
27+
{{ periph }}->sFilterRegister[{{ fb.bank_idx }}].FR1 = (({{ m1_macro }}) << 21);
28+
{% endif %}
29+
{% if fb.msg2 %}
30+
{% set m2_macro = fb.msg2.macro_name ~ "_MSG_ID" %}
31+
{% if fb.is_ext2 %}
32+
{{ periph }}->sFilterRegister[{{ fb.bank_idx }}].FR2 = (({{ m2_macro }}) << 3) | 4;
33+
{% else %}
34+
{{ periph }}->sFilterRegister[{{ fb.bank_idx }}].FR2 = (({{ m2_macro }}) << 21);
35+
{% endif %}
36+
{% else %}
37+
{% if fb.is_ext1 %}
38+
{{ periph }}->sFilterRegister[{{ fb.bank_idx }}].FR2 = (({{ m1_macro }}) << 3) | 4;
39+
{% else %}
40+
{{ periph }}->sFilterRegister[{{ fb.bank_idx }}].FR2 = (({{ m1_macro }}) << 21);
41+
{% endif %}
42+
{% endif %}
43+
{% endfor %}
44+
{% endif %}
45+
}

common/can_library/canpiler/templates/can_router.h.jinja

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,4 +19,4 @@
1919
#endif
2020
{% endif %}
2121

22-
#endif
22+
#endif // CAN_ROUTER_H

common/can_library/canpiler/templates/can_types.h.jinja

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,4 +19,4 @@ typedef enum {% if config.base_type %}: {{ config.base_type }}{% endif %} {
1919
} {{ name }};
2020

2121
{% endfor %}
22-
#endif
22+
#endif // CAN_TYPES_H

common/can_library/canpiler/templates/fault_data.h.jinja

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,4 +42,4 @@ extern const char* const fault_strings[TOTAL_NUM_FAULTS];
4242
void tx_fault_sync(void);
4343
void tx_fault_event(fault_index_t idx, uint16_t value);
4444

45-
#endif
45+
#endif // FAULT_DATA_H
Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
// FDCAN filter setup for {{ periph }}
2+
static inline void {{ periph }}_set_filters() {
3+
{% set fdcan_filt = mapping.fdcan_filters.get(periph) %}
4+
{% set accept_all = mapping.accept_all.get(periph, False) %}
5+
{% if accept_all %}
6+
// Accept all messages - filters configured in PHAL_FDCAN_init() by default
7+
(void)0;
8+
{% elif fdcan_filt and (fdcan_filt.std_ids or fdcan_filt.ext_ids) %}
9+
{% if fdcan_filt.std_ids %}
10+
static uint32_t sid_list[] = {
11+
{% for msg in fdcan_filt.std_ids %}
12+
{{ msg.macro_name }}_MSG_ID{{ "," if not loop.last }}
13+
{% endfor %}
14+
};
15+
{% endif %}
16+
17+
{% if fdcan_filt.ext_ids %}
18+
static uint32_t xid_list[] = {
19+
{% for msg in fdcan_filt.ext_ids %}
20+
{{ msg.macro_name }}_MSG_ID{{ "," if not loop.last }}
21+
{% endfor %}
22+
};
23+
{% endif %}
24+
25+
PHAL_FDCAN_setFilters(
26+
{{ periph }},
27+
{% if fdcan_filt.std_ids %}
28+
sid_list, {{ fdcan_filt.std_ids|length }},
29+
{% else %}
30+
NULL, 0,
31+
{% endif %}
32+
{% if fdcan_filt.ext_ids %}xid_list,
33+
{{ fdcan_filt.ext_ids|length }}
34+
{% else %}
35+
NULL, 0
36+
{% endif %}
37+
);
38+
{% else %}
39+
// No filters configured
40+
(void)0;
41+
{% endif %}
42+
}

common/can_library/canpiler/templates/node_header.h.jinja

Lines changed: 4 additions & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -159,83 +159,12 @@ static inline void CAN_SEND_{{ tx_msg.name }}(
159159
// Filter configuration
160160
{% for periph in peripherals %}
161161
{% if periph.startswith("FDCAN") %}
162-
// FDCAN filter setup for {{ periph }}
163-
static inline void {{ periph }}_set_filters() {
164-
{% set fdcan_filt = mapping.fdcan_filters.get(periph) %}
165-
{% set accept_all = mapping.accept_all.get(periph, False) %}
166-
{% if accept_all %}
167-
// Accept all messages - filters configured in PHAL_FDCAN_init() by default
168-
(void)0;
169-
{% elif fdcan_filt and (fdcan_filt.std_ids or fdcan_filt.ext_ids) %}
170-
{% if fdcan_filt.std_ids %}
171-
static uint32_t sid_list[] = {
172-
{% for msg in fdcan_filt.std_ids %}
173-
{{ msg.macro_name }}_MSG_ID{{ "," if not loop.last }}
174-
{% endfor %}
175-
};
176-
{% endif %}
177-
{% if fdcan_filt.ext_ids %}
178-
static uint32_t xid_list[] = {
179-
{% for msg in fdcan_filt.ext_ids %}
180-
{{ msg.macro_name }}_MSG_ID{{ "," if not loop.last }}
181-
{% endfor %}
182-
};
183-
{% endif %}
184-
PHAL_FDCAN_setFilters({{ periph }},
185-
{% if fdcan_filt.std_ids %}sid_list, {{ fdcan_filt.std_ids|length }}{% else %}NULL, 0{% endif %},
186-
{% if fdcan_filt.ext_ids %}xid_list, {{ fdcan_filt.ext_ids|length }}{% else %}NULL, 0{% endif %});
187-
{% else %}
188-
// No filters configured
189-
(void)0;
190-
{% endif %}
191-
}
192-
{% else %}
193-
// bxCAN filter setup for {{ periph }}
194-
static inline void {{ periph }}_set_filters() {
195-
{% set banks = mapping.filters.get(periph, []) %}
196-
{% set accept_all = mapping.accept_all.get(periph, False) %}
197-
{% if not banks and not accept_all %}
198-
return;
199-
{% elif accept_all %}
200-
// Accept all messages
201-
{% set bank_idx = 0 if periph == "CAN1" else 14 %}
202-
{{ periph }}->FM1R &= ~(1 << {{ bank_idx }}); // Mask mode
203-
{{ periph }}->FS1R |= (1 << {{ bank_idx }}); // 32-bit scale
204-
{{ periph }}->FA1R |= (1 << {{ bank_idx }});
205-
{{ periph }}->sFilterRegister[{{ bank_idx }}].FR1 = 0;
206-
{{ periph }}->sFilterRegister[{{ bank_idx }}].FR2 = 0;
207-
{% else %}
208-
{{ periph }}->FM1R |= 0x07FFFFFF; // Set banks 0-27 to id mode
209-
{{ periph }}->FS1R |= 0x07FFFFFF; // Set banks 0-27 to 32-bit scale
162+
{% include "fdcan_filter.c.jinja" %}
210163

211-
{% for fb in banks %}
212-
// Bank {{ fb.bank_idx }}: {{ fb.msg1.name }}{% if fb.msg2 %}, {{ fb.msg2.name }}{% endif %}
164+
{% else %}
165+
{% include "bxcan_filter.c.jinja" %}
213166

214-
{{ periph }}->FA1R |= (1 << {{ fb.bank_idx }});
215-
{% set m1_macro = fb.msg1.macro_name ~ "_MSG_ID" %}
216-
{% if fb.is_ext1 %}
217-
{{ periph }}->sFilterRegister[{{ fb.bank_idx }}].FR1 = (({{ m1_macro }}) << 3) | 4;
218-
{% else %}
219-
{{ periph }}->sFilterRegister[{{ fb.bank_idx }}].FR1 = (({{ m1_macro }}) << 21);
220-
{% endif %}
221-
{% if fb.msg2 %}
222-
{% set m2_macro = fb.msg2.macro_name ~ "_MSG_ID" %}
223-
{% if fb.is_ext2 %}
224-
{{ periph }}->sFilterRegister[{{ fb.bank_idx }}].FR2 = (({{ m2_macro }}) << 3) | 4;
225-
{% else %}
226-
{{ periph }}->sFilterRegister[{{ fb.bank_idx }}].FR2 = (({{ m2_macro }}) << 21);
227-
{% endif %}
228-
{% else %}
229-
{% if fb.is_ext1 %}
230-
{{ periph }}->sFilterRegister[{{ fb.bank_idx }}].FR2 = (({{ m1_macro }}) << 3) | 4;
231-
{% else %}
232-
{{ periph }}->sFilterRegister[{{ fb.bank_idx }}].FR2 = (({{ m1_macro }}) << 21);
233-
{% endif %}
234-
{% endif %}
235-
{% endfor %}
236-
{% endif %}
237-
}
238167
{% endif %}
239168
{% endfor %}
240169

241-
#endif
170+
#endif // {{ node.name|upper }}_H

0 commit comments

Comments
 (0)