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Zepp-HanzjRbb666
Zepp-Hanzj
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[arm][cortex-m4] Add hardware stack guard support
Enable RT_USING_HW_STACK_GUARD on Cortex-M4, which was previously only available on Cortex-M7 and Cortex-M33. Core porting (libcpu/arm/cortex-m4/): - Add mpu.c/mpu.h/mputype.h aligned with the Cortex-M7 MPU layer. The only difference is the default memory type attribute: Cortex-M4 has no L1 cache, so the cacheability bits are reduced to three cases. - Add rt_hw_stack_guard_init() to cpuport.c. - Add missing #include <rtconfig.h> to context_gcc.S and invoke rt_hw_mpu_table_switch() in the PendSV context switch path. - Update SConscript to exclude mpu.c when memory protection is disabled. BSP reference (bsp/stm32/stm32f407-fk407m2-zgt6/): - board.h: include rtthread.h and define NUM_STATIC_REGIONS. - board.c: define static_regions[] marking the Flash region read-only, guarded by RT_USING_MEM_PROTECTION so it is not enabled by default.
1 parent 45679c7 commit e2e6245

8 files changed

Lines changed: 607 additions & 117 deletions

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‎bsp/stm32/stm32f407-fk407m2-zgt6/board/board.c‎

Lines changed: 53 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -11,50 +11,61 @@
1111
#include <board.h>
1212
#include <drv_common.h>
1313

14+
#ifdef RT_USING_MEM_PROTECTION
15+
#include "mprotect.h"
16+
17+
rt_mem_region_t static_regions[NUM_STATIC_REGIONS] = {
18+
/* Flash region, read only */
19+
{
20+
.start = (void *)STM32_FLASH_START_ADRESS,
21+
.size = (rt_size_t)STM32_FLASH_SIZE,
22+
.attr = RT_MEM_REGION_P_RX_U_RX,
23+
},
24+
};
25+
#endif
26+
1427
void SystemClock_Config(void)
1528
{
16-
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
17-
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
18-
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
29+
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
30+
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
31+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
1932

20-
/**Configure the main internal regulator output voltage
21-
*/
22-
__HAL_RCC_PWR_CLK_ENABLE();
23-
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
24-
/**Initializes the CPU, AHB and APB busses clocks
25-
*/
26-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
27-
|RCC_OSCILLATORTYPE_LSE;
28-
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
29-
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
30-
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
31-
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
32-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
33-
RCC_OscInitStruct.PLL.PLLM = 4;
34-
RCC_OscInitStruct.PLL.PLLN = 168;
35-
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
36-
RCC_OscInitStruct.PLL.PLLQ = 7;
37-
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
38-
{
39-
Error_Handler();
40-
}
41-
/**Initializes the CPU, AHB and APB busses clocks
42-
*/
43-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
44-
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
45-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
46-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
47-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
48-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
33+
/**Configure the main internal regulator output voltage
34+
*/
35+
__HAL_RCC_PWR_CLK_ENABLE();
36+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
37+
/**Initializes the CPU, AHB and APB busses clocks
38+
*/
39+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
40+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
41+
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
42+
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
43+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
44+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
45+
RCC_OscInitStruct.PLL.PLLM = 4;
46+
RCC_OscInitStruct.PLL.PLLN = 168;
47+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
48+
RCC_OscInitStruct.PLL.PLLQ = 7;
49+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
50+
{
51+
Error_Handler();
52+
}
53+
/**Initializes the CPU, AHB and APB busses clocks
54+
*/
55+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
56+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
57+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
58+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
59+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
4960

50-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
51-
{
52-
Error_Handler();
53-
}
54-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
55-
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
56-
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
57-
{
58-
Error_Handler();
59-
}
61+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
62+
{
63+
Error_Handler();
64+
}
65+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
66+
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
67+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
68+
{
69+
Error_Handler();
70+
}
6071
}

‎bsp/stm32/stm32f407-fk407m2-zgt6/board/board.h‎

Lines changed: 15 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -11,31 +11,36 @@
1111
#ifndef __BOARD_H__
1212
#define __BOARD_H__
1313

14+
#include <rtthread.h>
1415
#include <stm32f4xx.h>
1516

1617
#ifdef __cplusplus
1718
extern "C" {
1819
#endif
1920

20-
#define STM32_SRAM_SIZE (128)
21-
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
21+
#define STM32_SRAM_SIZE (128)
22+
#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
2223

23-
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
24-
#define STM32_FLASH_SIZE (1024 * 1024)
25-
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
24+
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
25+
#define STM32_FLASH_SIZE (1024 * 1024)
26+
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
2627

2728
#if defined(__ARMCC_VERSION)
2829
extern int Image$$RW_IRAM1$$ZI$$Limit;
29-
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
30+
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
3031
#elif __ICCARM__
31-
#pragma section="CSTACK"
32-
#define HEAP_BEGIN (__segment_end("CSTACK"))
32+
#pragma section = "CSTACK"
33+
#define HEAP_BEGIN (__segment_end("CSTACK"))
3334
#else
3435
extern int __bss_end;
35-
#define HEAP_BEGIN ((void *)&__bss_end)
36+
#define HEAP_BEGIN ((void *)&__bss_end)
3637
#endif
3738

38-
#define HEAP_END STM32_SRAM_END
39+
#define HEAP_END STM32_SRAM_END
40+
41+
#ifdef RT_USING_MEM_PROTECTION
42+
#define NUM_STATIC_REGIONS 1
43+
#endif
3944

4045
void SystemClock_Config(void);
4146

‎libcpu/arm/cortex-m4/SConscript‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,19 @@ if rtconfig.PLATFORM in ['gcc', 'llvm-arm']:
2121
if rtconfig.PLATFORM in ['iccarm']:
2222
src += Glob('*_iar.S')
2323

24+
using_mpu = (
25+
GetDepend('RT_USING_MEM_PROTECTION') or
26+
GetDepend('RT_USING_HW_STACK_GUARD')
27+
)
28+
29+
if using_mpu:
30+
if rtconfig.PLATFORM not in ['gcc', 'llvm-arm']:
31+
raise RuntimeError(
32+
'Cortex-M4 memory protection currently supports GCC only'
33+
)
34+
else:
35+
SrcRemove(src, 'mpu.c')
36+
2437
group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
2538

2639
Return('group')

‎libcpu/arm/cortex-m4/context_gcc.S‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,8 @@
1818
*/
1919
/*@{*/
2020

21+
#include <rtconfig.h>
22+
2123
.cpu cortex-m4
2224
.syntax unified
2325
.thumb
@@ -155,6 +157,13 @@ switch_to_thread:
155157
BICNE lr, lr, #0x10 /* lr &= ~(1 << 4), set FPCA. */
156158
#endif
157159

160+
#if defined (RT_USING_MEM_PROTECTION)
161+
PUSH {r0-r3, r12, lr}
162+
BL rt_thread_self
163+
BL rt_hw_mpu_table_switch
164+
POP {r0-r3, r12, lr}
165+
#endif
166+
158167
pendsv_exit:
159168
/* restore interrupt */
160169
MSR PRIMASK, r2

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