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Merge pull request #171 from Silimate/infer_icg
infer_icg pass
2 parents 7ea578a + 2bb1083 commit d3c5591

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‎passes/silimate/Makefile.inc‎

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@@ -21,6 +21,7 @@ OBJS += passes/silimate/cone_partition.o
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OBJS += passes/silimate/clkmerge.o
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OBJS += passes/silimate/opt_boundary.o
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OBJS += passes/silimate/opt_vps.o
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OBJS += passes/silimate/infer_icg.o
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OBJS += passes/silimate/opt_expand.o
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GENFILES += passes/silimate/peepopt_expand.h

‎passes/silimate/infer_icg.cc‎

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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2026 Silimate Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct InferIcgPass : public Pass {
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InferIcgPass() : Pass("infer_icg", "infer $icg cells from latch-based clock gates") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" infer_icg [selection]\n");
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log("\n");
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log("This pass recognizes latch-based integrated clock gate structures and\n");
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log("replaces the gated-clock output with an internal $icg cell.\n");
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log("\n");
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log("The recognized positive-edge pattern is a one-bit $dlatch that is\n");
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log("transparent while the clock is low, feeding a one-bit $and or $logic_and\n");
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log("with the same clock. The latch can be active-low on the clock or\n");
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log("active-high on an inverted copy of the clock.\n");
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log("\n");
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log("The complementary high-idle pattern is also recognized: a latch that is\n");
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log("transparent while the clock is high, feeding a one-bit $or or $logic_or\n");
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log("with the same clock and an inverted latched enable. This is rewritten as\n");
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log("a $icg on the inverted clock plus an output inverter.\n");
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log("\n");
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log("The scan-enable leg is optional. If the effective latch data is driven\n");
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log("by a one-bit $or or $logic_or, its inputs are used as the $icg EN and\n");
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log("SE ports; otherwise the data is used as EN and SE is tied low.\n");
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log("\n");
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}
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static bool is_one_bit_binary(Cell *cell)
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{
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return cell->getParam(ID::A_WIDTH).as_int() == 1 &&
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cell->getParam(ID::B_WIDTH).as_int() == 1 &&
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cell->getParam(ID::Y_WIDTH).as_int() == 1;
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}
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static bool is_and(Cell *cell)
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{
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return cell->type.in(ID($and), ID($logic_and)) && is_one_bit_binary(cell);
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}
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static bool is_or(Cell *cell)
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{
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return cell->type.in(ID($or), ID($logic_or)) && is_one_bit_binary(cell);
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}
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static bool is_not(Cell *cell)
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{
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if (cell->type == ID($_NOT_))
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return true;
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return cell->type.in(ID($not), ID($logic_not)) &&
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cell->getParam(ID::A_WIDTH).as_int() == 1 &&
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cell->getParam(ID::Y_WIDTH).as_int() == 1;
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}
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static void add_driver(dict<SigBit, Cell *> &drivers, pool<SigBit> &multi_driver_bits, SigMap &sigmap, Cell *cell)
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{
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for (auto &conn : cell->connections()) {
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if (!cell->output(conn.first))
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continue;
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for (auto bit : sigmap(conn.second)) {
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if (bit.is_wire()) {
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if (drivers.count(bit) && drivers.at(bit) != cell)
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multi_driver_bits.insert(bit);
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else
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drivers[bit] = cell;
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}
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}
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}
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}
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static bool get_driver(dict<SigBit, Cell *> &drivers, pool<SigBit> &multi_driver_bits, SigMap &sigmap, SigSpec sig, Cell *&driver)
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{
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sig = sigmap(sig);
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if (GetSize(sig) != 1 || !sig[0].is_wire() || multi_driver_bits.count(sig[0]) || !drivers.count(sig[0]))
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return false;
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driver = drivers.at(sig[0]);
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return true;
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}
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static bool same_sig(SigMap &sigmap, SigSpec a, SigSpec b)
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{
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return sigmap(a) == sigmap(b);
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}
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static bool get_not_input(dict<SigBit, Cell *> &drivers, pool<SigBit> &multi_driver_bits, SigMap &sigmap,
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SigSpec sig, SigSpec &input, Cell *&not_cell)
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{
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Cell *driver = nullptr;
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if (!get_driver(drivers, multi_driver_bits, sigmap, sig, driver) || !is_not(driver))
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return false;
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not_cell = driver;
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input = sigmap(driver->getPort(ID::A));
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return true;
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}
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static bool latch_transparent_when(Cell *latch, SigSpec clk, bool high_when_transparent,
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dict<SigBit, Cell *> &drivers, pool<SigBit> &multi_driver_bits, SigMap &sigmap)
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{
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SigSpec latch_en = sigmap(latch->getPort(ID::EN));
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bool latch_en_pol = latch->getParam(ID::EN_POLARITY).as_bool();
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if (same_sig(sigmap, latch_en, clk))
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return latch_en_pol == high_when_transparent;
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SigSpec inv_input;
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Cell *not_cell = nullptr;
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if (get_not_input(drivers, multi_driver_bits, sigmap, latch_en, inv_input, not_cell) &&
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same_sig(sigmap, inv_input, clk))
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return latch_en_pol != high_when_transparent;
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return false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing INFER_ICG pass (infer $icg cells from latch-based clock gates).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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break;
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extra_args(args, argidx, design);
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int total_count = 0;
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for (auto module : design->selected_modules()) {
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SigMap sigmap(module);
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dict<SigBit, Cell *> drivers;
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pool<SigBit> multi_driver_bits;
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dict<SigBit, int> users;
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pool<Cell *> selected_cells;
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for (auto wire : module->wires())
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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if (bit.is_wire())
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users[bit]++;
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for (auto cell : module->cells()) {
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if (design->selected(module, cell))
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selected_cells.insert(cell);
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add_driver(drivers, multi_driver_bits, sigmap, cell);
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for (auto &conn : cell->connections()) {
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if (!cell->input(conn.first))
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continue;
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for (auto bit : sigmap(conn.second))
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if (bit.is_wire())
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users[bit]++;
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}
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}
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struct Match {
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Cell *gate_cell;
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Cell *latch;
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Cell *enable_or_cell;
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SigSpec clk;
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SigSpec en;
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SigSpec se;
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SigSpec gclk;
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SigSpec latched_en;
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bool invert_clk_and_gclk;
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};
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std::vector<Match> matches;
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pool<Cell *> consumed_gate_cells;
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for (auto gate_cell : module->selected_cells()) {
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if (consumed_gate_cells.count(gate_cell) || (!is_and(gate_cell) && !is_or(gate_cell)))
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continue;
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bool gate_is_and = is_and(gate_cell);
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SigSpec gate_a = sigmap(gate_cell->getPort(ID::A));
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SigSpec gate_b = sigmap(gate_cell->getPort(ID::B));
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SigSpec gclk = gate_cell->getPort(ID::Y);
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for (int clk_port = 0; clk_port < 2; clk_port++) {
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SigSpec clk = clk_port == 0 ? gate_a : gate_b;
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SigSpec latched_en = clk_port == 0 ? gate_b : gate_a;
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Cell *latch = nullptr;
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bool invert_clk_and_gclk = false;
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if (!gate_is_and) {
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SigSpec not_input;
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Cell *not_cell = nullptr;
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if (!get_not_input(drivers, multi_driver_bits, sigmap, latched_en, not_input, not_cell))
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continue;
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latched_en = not_input;
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invert_clk_and_gclk = true;
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}
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if (!get_driver(drivers, multi_driver_bits, sigmap, latched_en, latch))
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continue;
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if (!selected_cells.count(latch) || latch->type != ID($dlatch))
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continue;
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if (latch->getParam(ID::WIDTH).as_int() != 1)
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continue;
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if (!latch_transparent_when(latch, clk, !gate_is_and, drivers, multi_driver_bits, sigmap))
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continue;
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SigSpec latch_d = sigmap(latch->getPort(ID::D));
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SigSpec en = latch_d, se = State::S0;
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Cell *enable_or_cell = nullptr;
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if (get_driver(drivers, multi_driver_bits, sigmap, latch_d, enable_or_cell) &&
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selected_cells.count(enable_or_cell) && is_or(enable_or_cell)) {
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en = sigmap(enable_or_cell->getPort(ID::A));
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se = sigmap(enable_or_cell->getPort(ID::B));
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} else {
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enable_or_cell = nullptr;
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}
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matches.push_back({gate_cell, latch, enable_or_cell, clk, en, se, gclk, latched_en, invert_clk_and_gclk});
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consumed_gate_cells.insert(gate_cell);
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break;
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}
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}
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for (auto &match : matches) {
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Cell *cell = match.gate_cell;
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Cell *icg = module->addCell(NEW_ID2_SUFFIX("icg"), ID($icg));
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SigSpec icg_clk = match.clk;
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SigSpec icg_gclk = match.gclk;
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if (match.invert_clk_and_gclk) {
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icg_clk = module->Not(NEW_ID2_SUFFIX("icg_clk_n"), match.clk);
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icg_gclk = module->addWire(NEW_ID2_SUFFIX("icg_gclk"));
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}
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icg->setPort(ID::CLK, icg_clk);
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icg->setPort(ID::EN, match.en);
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icg->setPort(ID::SE, match.se);
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icg->setPort(ID::GCLK, icg_gclk);
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icg->add_strpool_attribute(ID::src, match.gate_cell->get_strpool_attribute(ID::src));
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icg->add_strpool_attribute(ID::src, match.latch->get_strpool_attribute(ID::src));
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if (match.enable_or_cell)
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icg->add_strpool_attribute(ID::src, match.enable_or_cell->get_strpool_attribute(ID::src));
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if (match.invert_clk_and_gclk)
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module->addNot(NEW_ID2_SUFFIX("icg_gclk_n"), icg_gclk, match.gclk, false, match.gate_cell->get_src_attribute());
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log("Inferred $icg cell %s.%s from latch %s and gate %s.\n",
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log_id(module), log_id(icg), log_id(match.latch), log_id(match.gate_cell));
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module->remove(match.gate_cell);
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SigSpec latched_en = sigmap(match.latched_en);
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if (GetSize(latched_en) == 1 && latched_en[0].is_wire() && users[latched_en[0]] == 1) {
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module->remove(match.latch);
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if (match.enable_or_cell) {
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SigSpec or_y = sigmap(match.enable_or_cell->getPort(ID::Y));
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if (GetSize(or_y) == 1 && or_y[0].is_wire() && users[or_y[0]] == 1)
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module->remove(match.enable_or_cell);
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}
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}
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total_count++;
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}
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}
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log("Inferred %d $icg cells.\n", total_count);
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}
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} InferIcgPass;
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PRIVATE_NAMESPACE_END

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