DU compile is working now!

Author: SpenceKonde

.github/workflows/compile-examples.yml

@@ -229,9 +229,10 @@ jobs:
             flash-class: 128
           - device-family: eb
             flash-class: 64
-          # Only headers for 16EB released.
           - device-family: eb
-            flash-class: 32
+            pincount: 64
+          - device-family: eb
+            pincount: 48
           # ugly Dx/Ex hack. Dx excludes 20 MHz internal osc, Ex 24 MHz.
           - int-osc: 20
             device-family: da
@@ -304,8 +305,6 @@ jobs:
           - overclock-osc: 16
             device-family: ea
             clocksource: extclock
-          - device-family: eb
-          - device-family: du
     steps:
       - name: Checkout repository
         uses: actions/checkout@v4

ChangeLog.md

@@ -8,7 +8,7 @@ These items are in addition to what was listed under changes already in release.
 * Enhancement: We need pinout diagrams for DU-series too!
 * Enhancement: We need pinout diagrams for EB-series too!
 * Enhancement: AVRdude ~7.2~ 8.0 out.
-* Bugfix: Make serialupdi work with EA, EB **CRITICAL**
+* ~Bugfix: Make serialupdi work with EA, EB **CRITICAL**~ Donq
 * Enhancement: Implement sleep library
 * Re-add SPI attach and detach.
 * Ensure libraries in sync with megaTinyCore.
@@ -32,6 +32,8 @@ These items are in addition to what was listed under changes already in release.
 * Remove the UPDI as GPIO pin option from non-optiboot parts because an analysis revealed that there was no configuration in which DxCore could be used in it's present form with the UPDI as GPIO option selected could be used with supported hardwae to prodice results other than bricked chips that core and supported hardware is unable to recover. Accordingly, these options should not be left as traps for the unwary.
 * Major documentation improvements focusing on main README.md.
 * Major documentation improvements focusing on Ref_Analog and Ref_Interrupts, the latter of which was previously the same file from megaTinyCore.
+* Correct bug in ADC init code that set Ex-series parts to the wrong ADC clock speed.
+*
 
 ### 1.5.11 (Emergency fix)
 * At some point in the recent past, I must have angered the gods of C, and suddenly millis disabled stopped working - the system would hang (actually, with in-depth investigation, it was shown to be bootlooping - before it called init(), it was calling 0x0000 (a dirty reset) instead of eliding a weakly defined function with nothing in the body except a return, or with an empty body. Why was it doing this? And why only when millis was disabled?). millis disabled is a key piece of core functionality, necessitating an urgent fix. Moving the definitions into main.cpp resolved this issue. (#485)

megaavr/cores/dxcore/UART0.cpp

@@ -83,7 +83,8 @@
     }
   #endif
 
-  #if !(defined(USE_ASM_RXC) && (USE_ASM_RXC == 1 || USE_ASM_RXC == 2) && (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16) /* && defined(USART1)*/)
+  #if !(defined(USE_ASM_RXC) && (USE_ASM_RXC == 1 || USE_ASM_RXC == 2) && \
+       (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16) /* && defined(USART1)*/)
     ISR(USART0_RXC_vect) {
       HardwareSerial::_rx_complete_irq(Serial);
     }

megaavr/cores/dxcore/UART1.cpp

@@ -55,7 +55,8 @@
     }
   #endif
 
-  #if !(defined(USE_ASM_RXC) && (USE_ASM_RXC == 1 || USE_ASM_RXC == 2) && (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16) /* && defined(USART1)*/)
+  #if !(defined(USE_ASM_RXC) && (USE_ASM_RXC == 1 || USE_ASM_RXC == 2) && \
+      (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16))
     ISR(USART1_RXC_vect) {
       HardwareSerial::_rx_complete_irq(Serial1);
     }

megaavr/cores/dxcore/UART2.cpp

@@ -59,9 +59,10 @@
     }
   #endif
 
-  #if !(defined(USE_ASM_RXC) && (USE_ASM_RXC == 1 || USE_ASM_RXC == 2) && (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16) /* && defined(USART1)*/)
+  #if !(defined(USE_ASM_RXC) && (USE_ASM_RXC == 1 || USE_ASM_RXC == 2) && \
+    (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16))
     ISR(USART2_RXC_vect) {
-      HardwareSerial::_rx_complete_irq(Serial);
+      HardwareSerial::_rx_complete_irq(Serial2);
     }
   #else
       ISR(USART2_RXC_vect, ISR_NAKED) {

megaavr/cores/dxcore/UART3.cpp

@@ -59,9 +59,10 @@
     }
   #endif
 
-  #if !(defined(USE_ASM_RXC) && (USE_ASM_RXC == 1 || USE_ASM_RXC == 2) && (SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16) /* && defined(USART1)*/)
+  #if !(defined(USE_ASM_RXC) && (USE_ASM_RXC == 1 || USE_ASM_RXC == 2) && \
+      (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16))
     ISR(USART3_RXC_vect) {
-      HardwareSerial::_rx_complete_irq(Serial);
+      HardwareSerial::_rx_complete_irq(Serial3);
     }
   #else
       ISR(USART3_RXC_vect, ISR_NAKED) {
@@ -84,7 +85,7 @@
        (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16) && \
        (SERIAL_TX_BUFFER_SIZE == 256 || SERIAL_TX_BUFFER_SIZE == 128 || SERIAL_TX_BUFFER_SIZE == 64 || SERIAL_TX_BUFFER_SIZE == 32 || SERIAL_TX_BUFFER_SIZE == 16))
     ISR(USART3_DRE_vect) {
-      HardwareSerial::_tx_data_empty_irq(Serial);
+      HardwareSerial::_tx_data_empty_irq(Serial3);
     }
   #else
     ISR(USART3_DRE_vect, ISR_NAKED) {

megaavr/cores/dxcore/UART4.cpp

@@ -59,9 +59,10 @@
     }
   #endif
 
-  #if !(defined(USE_ASM_RXC) && (USE_ASM_RXC == 1 || USE_ASM_RXC == 2) && (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16) /* && defined(USART1)*/)
+  #if !(defined(USE_ASM_RXC) && (USE_ASM_RXC == 1 || USE_ASM_RXC == 2) && \
+      (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16))
     ISR(USART4_RXC_vect) {
-      HardwareSerial::_rx_complete_irq(Serial);
+      HardwareSerial::_rx_complete_irq(Serial4);
     }
   #else
       ISR(USART4_RXC_vect, ISR_NAKED) {
@@ -84,7 +85,7 @@
        (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16) && \
        (SERIAL_TX_BUFFER_SIZE == 256 || SERIAL_TX_BUFFER_SIZE == 128 || SERIAL_TX_BUFFER_SIZE == 64 || SERIAL_TX_BUFFER_SIZE == 32 || SERIAL_TX_BUFFER_SIZE == 16))
     ISR(USART4_DRE_vect) {
-      HardwareSerial::_tx_data_empty_irq(Serial);
+      HardwareSerial::_tx_data_empty_irq(Serial4);
     }
   #else
     ISR(USART4_DRE_vect, ISR_NAKED) {

megaavr/cores/dxcore/UART5.cpp

@@ -59,9 +59,10 @@
     }
   #endif
 
-  #if !(defined(USE_ASM_RXC) && (USE_ASM_RXC == 1 || USE_ASM_RXC == 2) && (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16) /* && defined(USART1)*/)
+  #if !(defined(USE_ASM_RXC) && (USE_ASM_RXC == 1 || USE_ASM_RXC == 2) && \
+  (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16))
     ISR(USART5_RXC_vect) {
-      HardwareSerial::_rx_complete_irq(Serial);
+      HardwareSerial::_rx_complete_irq(Serial5);
     }
   #else
       ISR(USART5_RXC_vect, ISR_NAKED) {
@@ -84,7 +85,7 @@
        (SERIAL_RX_BUFFER_SIZE == 256 || SERIAL_RX_BUFFER_SIZE == 128 || SERIAL_RX_BUFFER_SIZE == 64 || SERIAL_RX_BUFFER_SIZE == 32 || SERIAL_RX_BUFFER_SIZE == 16) && \
        (SERIAL_TX_BUFFER_SIZE == 256 || SERIAL_TX_BUFFER_SIZE == 128 || SERIAL_TX_BUFFER_SIZE == 64 || SERIAL_TX_BUFFER_SIZE == 32 || SERIAL_TX_BUFFER_SIZE == 16))
     ISR(USART5_DRE_vect) {
-      HardwareSerial::_tx_data_empty_irq(Serial);
+      HardwareSerial::_tx_data_empty_irq(Serial5);
     }
   #else
     ISR(USART5_DRE_vect, ISR_NAKED) {

megaavr/cores/dxcore/core_devices.h

@@ -1042,15 +1042,15 @@ DB silicon with die rev 0x11 is available.*/
   #define ADC_MAXIMUM_ACCUMULATE       (1024) // This allows the 5 extra bits of resolution
   #define ADC_RESULT_SIZE                (24)
   #define ADC_SIGNCHOPPING                (1) // if defined, sign chopping can be enabled
-#elif defined(ADC0_MUXNEG)                    /* I don't know what unofficial version to use. It's a *downgrade* of the v2.0 to capabilities below what I dubbed the 1.5 */
+#elif defined(ADC_LOWLAT_bm)
   #define ADC_VERSION                  (0xFA) // F'n A! The DU had it rough at the hands of the USB natives...
   #define ADC_DIFFERENTIAL                (0) // They took his differential mode!
-  #define ADC_MAX_OVERSAMPLED_RESOLUTION (13) // He can only remember 64 samples in accumulated mode (memory loss from repeated blows to the head)
-  #define ADC_NATIVE_RESOLUTION          (10) // and ah.. they took off two bits...    *I told him they weren't friendly...
-  #define ADC_NATIVE_RESOLUTION_LOW       (8)
-  #define ADC_MAXIMUM_ACCUMULATE       (1024) // This allows the 5 extra bits of resolution
-  #define ADC_RESULT_SIZE                (24)
-  #define ADC_SIGNCHOPPING                (1)
+  #define ADC_MAX_OVERSAMPLED_RESOLUTION (13) // Memory loss too - He can only remember 64 samples in accumulated mode...
+  #define ADC_NATIVE_RESOLUTION          (10) // and ah.. they took off two bits
+  #define ADC_NATIVE_RESOLUTION_LOW       (8) // *I told him they weren't friendly...
+  #define ADC_MAXIMUM_ACCUMULATE         (64)
+  #define ADC_RESULT_SIZE                (16)
+  #define ADC_SIGNCHOPPING                (0)
 
 #else                                         // Dx-series ADCs are less fancy.
   #define ADC_DIFFERENTIAL                (1) // Crapola differential ADC that is effectively kicking off two ADCs at once

megaavr/cores/dxcore/wiring.c

@@ -1891,12 +1891,55 @@ void nudge_millis(__attribute__((unused)) uint16_t nudgesize) {
 
 
 
-
 #if defined(ADC0)
   void __attribute__((weak)) init_ADC0() {
     ADC_t* pADC;
     _fastPtr_d(pADC, &ADC0);
-    #if !defined(ADC0_PGACTRL)
+
+    #if defined(ADC0_TEMP2) /* New/Good ADC 2.1 */
+      // Target = 2MHz, 2-6 MHz is only allowed   with Vdd or external as reference.
+      #if F_CPU      > 32000000             // 36 MHz /20  = 1.80 MHz
+        pADC->CTRLB  = ADC_PRESC_DIV20_gc;  // 33 MHz /20  = 1.67 MHz
+      #elif F_CPU   >  28000000             // 32 MHz /16  = 2.00 MHz
+        pADC->CTRLB  = ADC_PRESC_DIV16_gc;  // 28 MHz /16  = 1.75 MHz
+      #elif F_CPU   >  24000000             // 25 MHz /14  = 1.78 MHz
+        pADC->CTRLB  = ADC_PRESC_DIV14_gc;  // 24 MHz /12  = 2.00 MHz
+      #elif F_CPU   >  20000000
+        pADC->CTRLB  = ADC_PRESC_DIV10_gc;  // 20 MHz / 10  = 2.00 MHz
+      #elif F_CPU   > 16000000
+        pADC->CTRLB  = ADC_PRESC_DIV6_gc;   // 16 MHz / 8  = 2.00 MHz
+      #elif F_CPU   > 12000000
+        pADC->CTRLB  = ADC_PRESC_DIV4_gc;   // 12 MHz / 6 = 2.00 MHz
+      #elif F_CPU   >  6000000              // 10 MHz / 6  = 1.67 MHz
+        pADC->CTRLB  = ADC_PRESC_DIV4_gc;   //  8 MHz / 4 = 2.00 MHz
+      #else                                 //  5 MHz / 4 = 1.25 MHz
+        pADC->CTRLB  = ADC_PRESC_DIV2_gc;   //  4 MHz / 2 = 2.00 MHz
+      #endif                                //  1 MHz / 2 =  500 kHz
+      pADC->CTRLE = 15; // 15.5 without PGA, 16 with PGA, corresponding to 7.75 or 8 us.
+      pADC->CTRLA = ADC_ENABLE_bm | ADC_LOWLAT_bm;
+      pADC->PGACTRL = ADC_PGABIASSEL_75PCT_gc; // Default for PGA settings.
+    #elif defined(ADC_LOWLAT_bm) /* what version number comes between 1.5 and 2.0, but is after 2.1? */
+      #if F_CPU      > 32000000
+        pADC->CTRLB  = ADC_PRESC_DIV20_gc;  // 36 MHz /20  = 1.80 MHz
+      #elif F_CPU   >  28000000             // 33 MHz /20  = 1.67 MHz
+        pADC->CTRLB  = ADC_PRESC_DIV16_gc;  // 32 MHz /16  = 2.00 MHz
+      #elif F_CPU   >  24000000             // 28 MHz /16  = 1.75 MHz
+        pADC->CTRLB  = ADC_PRESC_DIV14_gc;  // 25 MHz /14  = 1.78 MHz
+      #elif F_CPU   >  20000000
+        pADC->CTRLB  = ADC_PRESC_DIV12_gc;  // 24 MHz /12  = 2.00 MHz
+      #elif F_CPU   > 16000000              // 20 MHz / 10  = 2.00 MHz
+        pADC->CTRLB  = ADC_PRESC_DIV10_gc;  // 16 MHz / 8  = 2.00 MHz
+      #elif F_CPU   > 12000000
+        pADC->CTRLB  = ADC_PRESC_DIV4_gc;   // 12 MHz / 6 = 2.00 MHz
+      #elif F_CPU   >  6000000              // 10 MHz / 6  = 1.67 MHz
+        pADC->CTRLB  = ADC_PRESC_DIV4_gc;   //  8 MHz / 4 = 2.00 MHz
+      #else                                 //  5 MHz / 4 = 1.25 MHz
+        pADC->CTRLB  = ADC_PRESC_DIV2_gc;   //  4 MHz / 2 = 2.00 MHz
+      #endif                                //  1 MHz / 2 =  500 kHz
+      pADC->CTRLE = 15; // 15.5 without PGA, 16 with PGA, corresponding to 7.75 or 8 us.
+      pADC->CTRLA = ADC_ENABLE_bm | ADC_LOWLAT_bm;
+    #else /* AVR DA/DB/DD */
+      // Target is again 2 MHz, the maximum the Dx is rated for.
       #if F_CPU >= 48000000
         pADC->CTRLC = ADC_PRESC_DIV48_gc; // 1 @ 48 MHz
       #elif F_CPU >  40000000
@@ -1932,43 +1975,14 @@ void nudge_millis(__attribute__((unused)) uint16_t nudgesize) {
         pADC->COMMAND = 0x01;
         pADC->COMMAND = 0x02;
       #endif
-
-    #else
-      /* On the 2-series maximum with internal reference is 3 MHz, so we will
-       * target highest speed that doesn't exceed that and 16 ADC clocks sample
-       * duration. */
-      #if F_CPU     > 32000000            // 36 MHz /14 = 2.57 MHz
-        pADC->CTRLB  = ADC_PRESC_DIV10_gc; // 33 MHz /14 = 2.35 MHz
-      #elif F_CPU  >= 30000000            // 32 MHz /12 = 2.67 MHz
-        pADC->CTRLB  = ADC_PRESC_DIV12_gc; // 30 MHz /12 = 2.50 MHz
-      #elif F_CPU  >= 24000000            // 25 MHz /10 = 2.50 MHz
-        pADC->CTRLB  = ADC_PRESC_DIV10_gc; // 24 MHz /10 = 2.40 MHz
-      #elif F_CPU  >= 20000000
-        pADC->CTRLB  = ADC_PRESC_DIV8_gc;  // 20 MHz / 8 = 2.50 MHz
-      #elif F_CPU  >= 16000000
-        pADC->CTRLB  = ADC_PRESC_DIV6_gc;  // 16 MHz / 6 = 2.67 MHz
-      #elif F_CPU  >= 12000000
-        pADC->CTRLB  = ADC_PRESC_DIV4_gc;  // 12 MHz / 4 = 3.00 MHz
-      #elif F_CPU  >=  6000000            // 10 MHz / 4 = 2.50 MHz
-        pADC->CTRLB  = ADC_PRESC_DIV4_gc;  //  8 MHz / 4 = 2.00 MHz
-      #else                               //  5 MHz / 2 = 2.50 MHz
-        pADC->CTRLB  = ADC_PRESC_DIV2_gc;  //  4 MHz / 2 = 2.00 MHz
-      #endif                              //  1 MHz / 2 =  500 kHz
-      pADC->CTRLE = 15; // 15.5 without PGA, 16 with PGA, corresponding to 7.75 or 8 us.
-      pADC->CTRLA = ADC_ENABLE_bm | ADC_LOWLAT_bm;
-      pADC->PGACTRL = ADC_PGABIASSEL_75PCT_gc;
-      /* Note that we don't *enable* it automatically in init().
-       * 3/4th bias is good up to 4.5 MHz CLK_ADC, 15 ADC Clocks to sample the PGA
-       * up to 5 MHz, so within the regime of speeds that have to be compatible
-       * with internal references, we are in the clear there. */
-    #endif
+    #endif // End EA/DU/Other selection
     analogReference(VDD);
     #if defined(DAC0)
       DACReference(VDD);
     #endif
   }
 #endif
-#if defined(ADC1)
+#if defined(ADC1) /* presently, only relevant for tiny1. */
   void __attribute__((weak)) init_ADC1() {
     ADC_t* pADC;
     _fastPtr_d(pADC, &ADC1);
@@ -1995,7 +2009,7 @@ void nudge_millis(__attribute__((unused)) uint16_t nudgesize) {
         pADC->CTRLC = ADC_PRESC_DIV2_gc;
       #endif
       pADC->SAMPCTRL = 14; // 16 ADC clock sampling time - should be about the same amount of *time* as originally?
-      // This is WAY conservative! We could drop it down...
+      // This is WAY conservative! You can drop it way down to speed up ADC reads if the source is reasonably low impedance. .
       pADC->CTRLD = ADC_INITDLY_DLY64_gc; // VREF can take 50uS to become ready, and we're running the ADC clock
       // at around 1 MHz, so we want 64 ADC clocks when we start up a new reference so we don't get bad readings at first
       /* Enable ADC */