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# DxCore - Arduino support for the AVR DA, DB, and DD-series
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Use the Table of Contents button! Why was I making a ToC manually? (especially since I apparently did it wrong..)
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# DxCore - Arduino support for the AVR DA, DB, and DD-series
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This is an Arduino core to support the AVR DA, DB, DD, EA, EB, and DU-series microcontrollers from Microchip. These parts are the latest and highest spec 8-bit AVRs available, and take the AVR architecture to a whole new level with up to 128k flash, 16k SRAM, 55 I/O pins, 6 UART ports, 2 SPI and I2C ports, type A/B/D timers, and enhanced pin interrupts.
Seems they've gotten most of the problems worked out, finally, other than the Dx-write endurance. 1000 rewrites is still enough though, and supposedly, the Dx-series parts meet the original (10k) spec at room temperature, just not over the whole temperature range (explaining why the problem had not been noticed for over a year)
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### Issues that we expected to see in errata, but have not yet seen:
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### Issues that we expected to see in errata, but have not yet seen
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#### The Vector Table was Wrong on very early AVR32DA, some of which escaped into the wild; these are not usable.
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Microchip recalled them, but some disties had already shipped some out.
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My only thought here is "If SPM instruction requires word aligned access, why not just require writes to be word addressed, and then you could forget about rampz except for the sole case of ELPM, and everone's life would be simpler". I would have no objection to losing ST/STS writes to the flash if it meant that I could take RAMPZ out of the equation while writing to the flash. Hell, imagine if ELPM assumed RAMPZ = 1 and LPM to assume RAMPZ = 0, and all the headaches caused by RAMPZ would be gone!
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### UPDI programming issue with 16-bit STS after 24-bit STptr (Datasheet should be clarrified)
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On parts which use 24-bit addressing, 16-bit addressing should not be used for STS operations. The results are profoundly baffling - the long and short of it is: See the table in the UPDI chapter, titled `Figure xx-10: STS Instruction Operation`? Cross out the top two lines. If STptr has been used with a 24-bit pointer (which you normally do to write the flash), if a subsequent STS doesn't use the 24-bit address, it will use the high byte from ptr!
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On parts which use 24-bit addressing, 16-bit addressing should not be used for STS operations. The results are profoundly baffling - the long and short of it is: See the table in the UPDI chapter, titled `Figure xx-10: STS Instruction Operation`? Cross out the top two lines. If STptr has been used with a 24-bit pointer (which you normally do to write the flash), if a subsequent STS doesn't use the 24-bit address, it will use the high byte from ptr! This behavior is apparently intended and expected, but that isn't communicated to the reader of the datasheet.
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## Errata and Datasheets
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Get the most up to date information from Microchip's website. They keep moving files around, so I'm just going to link their product pages.
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Finally, the USART had the two RS485 modes listed, like tinyAVR 0/1-series, instead of just the one. The second mode raised all sorts of questions about how the chip ought to behave - and was one of those terse-and-useless sections that answers little. If I correctly understand the intent - it was meant to listen to XDIRand only output data when XDIR was in the correct state. So what does it do when the pin transitioned to "no sending" state while it was in the middle of a byte? Is there any answer to that that will result in correct behavior in all applicable use-cases? I think they thought about that one, realized the answer was "probably not" after they re-read what they'd said about it in the datasheets of the parts that had been released a few times, and figured that they'd be better off not supporting that. It is unclear whether the feature is still present in the silicon. On the DA-series I suspect it is, and likely DB as well, as they don't appear to have touched the USART.
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## Ex-series
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Much less interesting... only one thing that wasn't supposed to be there was apparently left in, a section of NVMCTRL that configures the EEPROM writes. Oddly, the initial silicon's NVMCTRL was badly broken.
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Much less interesting... only one thing that wasn't supposed to be there was apparently left in, a section of NVMCTRL that configures the EEPROM writes. Oddly, the initial silicon's NVMCTRL was badly broken - but the EEPROM worked fine, it was the flash that was busted.
Copy file name to clipboardExpand all lines: megaavr/libraries/EEPROM/README.md
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In the event of errors, we clear the errors.
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If the low error bit is set, (indicative of a problem with the command used), in order to return the NVMCTRL module to a usable state, this function will, in addition to clearing the error flags, reset CTRLA to 0/NOOP/None
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