I noticed tcl creates a new template that only allows .v files. Here's my file directory. What steps are involved in compiling the RTL Design and hardening it to a chip?
designs/enigma_cipher/
├── config.json
└── src
├── enigma.sv
├── plugboard.sv
├── reflector.sv
└── rotor.sv
1 directory, 5 files
config.json -
{
"DESIGN_NAME": "enigma",
"VERILOG_FILES": "dir::src/*v",
"CLOCK_PORT": "clk",
"CLOCK_PERIOD": 10.0,
"FP_PDN_MULTILAYER": true
}
I noticed tcl creates a new template that only allows .v files. Here's my file directory. What steps are involved in compiling the RTL Design and hardening it to a chip?
config.json -