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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# Date created = 12:05:05 July 10, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# greatest_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY greatest
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:05:05 JULY 10, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_location_assignment PIN_Y2 -to clk50
set_location_assignment PIN_AE5 -to sdram_clk
set_location_assignment PIN_AH26 -to tft_cs
set_location_assignment PIN_AD25 -to tft_dc
set_location_assignment PIN_AF20 -to tft_reset
set_location_assignment PIN_AF26 -to tft_sck
set_location_assignment PIN_AG25 -to tft_sdi
set_location_assignment PIN_AH22 -to tft_sdo
set_location_assignment PIN_AA5 -to sd_addr[11]
set_location_assignment PIN_R5 -to sd_addr[10]
set_location_assignment PIN_Y6 -to sd_addr[9]
set_location_assignment PIN_Y5 -to sd_addr[8]
set_location_assignment PIN_W7 -to sd_addr[6]
set_location_assignment PIN_AA7 -to sd_addr[7]
set_location_assignment PIN_W8 -to sd_addr[5]
set_location_assignment PIN_V5 -to sd_addr[4]
set_location_assignment PIN_P1 -to sd_addr[3]
set_location_assignment PIN_U8 -to sd_addr[2]
set_location_assignment PIN_V8 -to sd_addr[1]
set_location_assignment PIN_R6 -to sd_addr[0]
set_location_assignment PIN_AC2 -to sd_data[15]
set_location_assignment PIN_AB3 -to sd_data[14]
set_location_assignment PIN_AC1 -to sd_data[13]
set_location_assignment PIN_AB2 -to sd_data[12]
set_location_assignment PIN_AA3 -to sd_data[11]
set_location_assignment PIN_AB1 -to sd_data[10]
set_location_assignment PIN_Y4 -to sd_data[9]
set_location_assignment PIN_Y3 -to sd_data[8]
set_location_assignment PIN_U3 -to sd_data[7]
set_location_assignment PIN_V1 -to sd_data[6]
set_location_assignment PIN_V2 -to sd_data[5]
set_location_assignment PIN_V3 -to sd_data[4]
set_location_assignment PIN_W1 -to sd_data[3]
set_location_assignment PIN_V4 -to sd_data[2]
set_location_assignment PIN_W2 -to sd_data[1]
set_location_assignment PIN_W3 -to sd_data[0]
set_location_assignment PIN_R4 -to ba[1]
set_location_assignment PIN_U7 -to ba[0]
set_location_assignment PIN_W4 -to dqm[1]
set_location_assignment PIN_U2 -to dqm[0]
set_location_assignment PIN_U6 -to ras_n
set_location_assignment PIN_V6 -to we_n
set_location_assignment PIN_V7 -to cas_n
set_location_assignment PIN_AA6 -to Cke
set_location_assignment PIN_T4 -to cs_n
set_location_assignment PIN_AE16 -to data_cam[7]
set_location_assignment PIN_AD21 -to data_cam[6]
set_location_assignment PIN_Y16 -to data_cam[5]
set_location_assignment PIN_AC21 -to data_cam[4]
set_location_assignment PIN_Y17 -to data_cam[3]
set_location_assignment PIN_AB21 -to data_cam[2]
set_location_assignment PIN_AC15 -to data_cam[1]
set_location_assignment PIN_AB22 -to data_cam[0]
set_location_assignment PIN_AC22 -to HREF_cam
set_location_assignment PIN_AC19 -to PCLK_cam
set_location_assignment PIN_AF25 -to VSYNC_cam
set_location_assignment PIN_AF16 -to XCLK_cam
set_location_assignment PIN_AD19 -to on_off_cam
set_location_assignment PIN_AF15 -to res_cam
set_location_assignment PIN_AF24 -to sioc
set_location_assignment PIN_AE21 -to siod
set_location_assignment PIN_M23 -to rst
set_location_assignment PIN_H19 -to LED[7]
set_location_assignment PIN_J19 -to LED[6]
set_location_assignment PIN_E18 -to LED[5]
set_location_assignment PIN_F18 -to LED[4]
set_location_assignment PIN_F21 -to LED[3]
set_location_assignment PIN_E19 -to LED[2]
set_location_assignment PIN_F19 -to LED[1]
set_location_assignment PIN_G19 -to LED[0]
set_location_assignment PIN_M21 -to start_gray_kn
set_location_assignment PIN_AF22 -to r[4]
set_location_assignment PIN_AD22 -to g[5]
set_location_assignment PIN_AE22 -to b[4]
set_global_assignment -name QIP_FILE Sdram_Control_4Port/Sdram_WR_FIFO.qip
set_global_assignment -name QIP_FILE Sdram_Control_4Port/Sdram_RD_FIFO.qip
set_global_assignment -name SOURCE_FILE Sdram_Control_4Port/Sdram_Params.h
set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/Sdram_Control_4Port.v
set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/sdr_data_path.v
set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/control_interface.v
set_global_assignment -name VERILOG_FILE Sdram_Control_4Port/command.v
set_global_assignment -name SYSTEMVERILOG_FILE lcd/tft_ili9341_spi.sv
set_global_assignment -name SYSTEMVERILOG_FILE lcd/tft_ili9341.sv
set_global_assignment -name SYSTEMVERILOG_FILE lcd/hellosoc_top.sv
set_global_assignment -name VERILOG_FILE synt/cam_config/SCCB_interface.v
set_global_assignment -name VERILOG_FILE synt/cam_config/OV7670_config_rom.v
set_global_assignment -name VERILOG_FILE synt/cam_config/OV7670_config.v
set_global_assignment -name VERILOG_FILE synt/cam_config/camera_configure.v
set_global_assignment -name SYSTEMVERILOG_FILE synt/fsm_global.sv
set_global_assignment -name VERILOG_FILE synt/delay_rg.v
set_global_assignment -name QIP_FILE fifo_1024_16_camera.qip
set_global_assignment -name VERILOG_FILE greatest.v
set_global_assignment -name QIP_FILE pll_for_camera.qip
set_global_assignment -name QIP_FILE pll_for_sdram_controller.qip
set_global_assignment -name QIP_FILE fifo_big.qip
set_global_assignment -name VERILOG_FILE synt/cam_config/camera_read.v
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name VERILOG_FILE frame_done_delay.v
set_global_assignment -name QIP_FILE camera_data.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity cam_proj_top -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity cam_proj_top -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity cam_proj_top -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -entity cam_proj_top -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top