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Add LDA AbsoluteX addressing mode
1 parent 72f55a6 commit b8d8a3c

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Lines changed: 34 additions & 0 deletions

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crates/rmachine-core/src/machine.rs

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Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ pub enum Mode {
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ZeroPage,
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ZeroPageX,
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Absolute,
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AbsoluteX,
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Relative,
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}
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crates/rmachine-mos6502/src/instructions.rs

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@@ -785,6 +785,39 @@ pub const INSTRUCTIONS: &[Instruction] = &[
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assert!(m.test_bit("SR", NEGATIVE), "negative flag not set");
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},
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},
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Instruction {
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mnemonic: "LDA",
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mode: Mode::AbsoluteX,
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opcode: 0xBD,
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bytes: 3,
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cycles: 4,
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execute: |m| {
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let base = m.fetch16();
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let addr = base.wrapping_add(m.reg("XR").into());
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load_reg(m, "AC", m.get8(addr));
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},
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test: |m| {
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m.set8(0x0102, 0xFF);
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m.run_program(&[
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0xA2, 0x02, // $0000 LDX #$02
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0xBD, 0x00, 0x01, // $0002 LDA $0100,X
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0x00, // $0005 BRK
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]);
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assert_eq!(m.reg("AC"), 0xFF, "wrong AC");
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assert!(!m.test_bit("SR", ZERO), "zero flag not cleared");
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assert!(m.test_bit("SR", NEGATIVE), "negative flag not set");
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m.set8(0x0102, 0x00);
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m.run_program(&[
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0xA2, 0x02, // $0000 LDX #$02
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0xBD, 0x00, 0x01, // $0002 LDA $0100,X
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0x00, // $0005 BRK
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]);
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assert_eq!(m.reg("AC"), 0x00, "wrong AC");
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assert!(m.test_bit("SR", ZERO), "zero flag not set");
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assert!(!m.test_bit("SR", NEGATIVE), "negative flag not cleared");
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},
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},
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Instruction {
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mnemonic: "LDX",
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mode: Mode::Immediate,

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