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tfcollinstfcollins
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Add updates for 2x upsample rates and HDL hw checks
Signed-off-by: tfcollins <travisfcollins@gmail.com>
1 parent e9b6c64 commit 2160c7b

6 files changed

Lines changed: 295 additions & 2 deletions

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‎trx_examples/targeting/QPSKTxRxHDLExample/adrv9002_capture.m‎

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% clear all;
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%commhdlQPSKTxRxModelInit
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uri = 'ip:10.0.0.172';
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chan = 1;
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%% Tx set up
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tx = adi.ADRV9002.Tx('uri',uri);
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tx.DataSource = 'DMA';
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tx.EnableCyclicBuffers = true;
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tx.AttenuationChannel0 = -30;
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% tx.CenterFrequencyChannel0 = tx.CenterFrequencyChannel0 + 100e3;
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tx.CenterFrequencyChannel1 = tx.CenterFrequencyChannel0;
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tx.EnabledChannels = chan;
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% data = load('tx_capture.mat');
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% x = data.tx_capture.Data;
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frameSize = 2240;
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dataBits = reshape(repmat(randsrc(frameSize*1,1,[0,1],RandStream('mcg16807','Seed',0)), 59,1), [frameSize*59,1]);
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enabledScramble = false;
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[x,refQPSKSym] = generateQPSKTxReference(dataBits, enabledScramble);
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% x = randi(10,1024,1);
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x = x ./ max(abs(x));
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x = x.* 2^15;
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tx(x);
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pause(3);
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%% Rx set up
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rx = adi.ADRV9002.Rx('uri',uri);
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% rx.EnabledChannels = 1;
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rx.EnabledChannels = chan;
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rx.kernelBuffersCount = 1;
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N = 0;
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rx.CenterFrequencyChannel0 = tx.CenterFrequencyChannel0 + N;
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rx.CenterFrequencyChannel1 = tx.CenterFrequencyChannel0 + N;
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rx.SamplesPerFrame = 2^20;
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%% Run
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for k=1:30
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valid = false;
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while ~valid
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[y, valid] = rx();
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end
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end
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tx.release();
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rx.release();
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% figure(1);
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% plot(0:numel(y)-1, real(y), 'r', 0:numel(y)-1, imag(y), 'b');
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% xlim([0 250]);
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% xlabel('sample index');
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% grid on;
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%% To timeseries
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% Scale
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plot(real(y),imag(y));
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yy = double(y) ./ 2^13 * 3/2;
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% yy = yy(1:2^19);
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% Convert to timeseries Simulink can understand
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sampleTime = 1/(Rsym*Config.SamplesPerSymbol);
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% sampleTime = 1/1.92e6;
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numSteps = length(yy);
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time = sampleTime*[0:(numSteps-1)];
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data = yy;
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time = time';
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% data = data.';
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inputData = timeseries(data,time);
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save("rx_capture_adrv9002_hdl.mat","inputData","-v7.3");
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%%
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function [txWaveform,QPSKModSymbols] = generateQPSKTxReference(databits, enableScramble)
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% This function is a algorithmic equivalent of QPSK Tx subsystem
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% in commhdlQPSKTxRx.slx. This will not generate frame gaps between the
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% frames where as the Simulink model does.
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Params = commhdlQPSKTxRxParameters();
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Preamble = Params.Preamble;
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DataBitsPerPacket = Params.DataBitsPerPacket;
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RRCCoef = Params.RRCCoef;
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SamplesPerSymbol = Params.SamplesPerSymbol;
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dataBitsPacketWise = reshape(databits,DataBitsPerPacket,[]);
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ScrambledBitsPacketWise = zeros(size(dataBitsPacketWise));
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if enableScramble
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for packetNo = 1:size(dataBitsPacketWise,2)
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ScrambledBitsPacketWise(:,packetNo) = scramble(dataBitsPacketWise(:,packetNo));
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end
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else
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packetNo = size(dataBitsPacketWise,2);
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ScrambledBitsPacketWise = dataBitsPacketWise;
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end
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BitsPacketWise = [repmat(Preamble,1,packetNo);ScrambledBitsPacketWise];
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QPSKModSymbols = QPSKModulate(BitsPacketWise(:));
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txWaveform = zeros(length(QPSKModSymbols)*SamplesPerSymbol,1);
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txWaveform(1:SamplesPerSymbol:end) = QPSKModSymbols;
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txWaveform = filter(RRCCoef,1,txWaveform);
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end
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function QPSKMod = QPSKModulate(sdata)
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sdataI = sdata(1:2:end);
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sdataQ = sdata(2:2:end);
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QPSKMod = pskmod(sdataI*2+sdataQ,4,pi/4,'gray');
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end
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function output = scramble(input)
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scramblePoly = [1 0 0 1 0 0 0];
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init_state = [1 0 1 1 1 0 1];
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currentState = init_state;
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output = zeros(size(input));
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for i = 1:length(input)
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bit = mod(nnz(currentState(scramblePoly == 1)),2);
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output(i) = bitxor(input(i),bit);
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currentState(1) = currentState(2);
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currentState(2) = currentState(3);
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currentState(3) = currentState(4);
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currentState(4) = currentState(5);
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currentState(5) = currentState(6);
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currentState(6) = currentState(7);
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currentState(7) = bit;
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end
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end
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function [RxBits,trueOffset] = getBitsofCorrectSyncedPackets(rxOut,simTimingOffset,srtLoc,endLoc,payloadLen)
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data = cell(length(srtLoc),1);
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for i = 1:length(srtLoc)
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if any(srtLoc(i) == endLoc-payloadLen+1)
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data{i} = rxOut(srtLoc(i):srtLoc(i)+payloadLen-1);
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end
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end
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data = data(:);
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trueOffset = mode(simTimingOffset);
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RxBits = data;
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end
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‎trx_examples/targeting/QPSKTxRxHDLExample/commhdlQPSKTxRx.slx‎

5.58 KB
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‎trx_examples/targeting/QPSKTxRxHDLExample/commhdlQPSKTxRxModelInit.m‎

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% disp(isequal(a,b))
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%%
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dataBits = eval(get_param([gcs '/Input Data'],'dataBits'));
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Rsym = eval(get_param([gcs '/Input Data'],'Rsym'));
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dataBits = eval(get_param([gcs '/Transmitter/Input Data'],'dataBits'));
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Rsym = eval(get_param([gcs '/Transmitter/Input Data'],'Rsym'));
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validateattributes(dataBits,{'double'},{'binary','column','finite'},'','dataBits');
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validateattributes(Rsym,{'double'},{'finite','scalar','positive'},'','Rsym');
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‎trx_examples/targeting/QPSKTxRxHDLExample/hdlworkflow.m‎

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hdlset_param('commhdlQPSKTxRx/Transmitter/complex', 'IOInterface', 'No Interface Specified');
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hdlset_param('commhdlQPSKTxRx/Transmitter/complex', 'IOInterfaceMapping', '');
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% Set Outport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/msg_count_out', 'IOInterface', 'AXI4-Lite');
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hdlset_param('commhdlQPSKTxRx/Transmitter/msg_count_out', 'IOInterfaceMapping', 'x"104"');
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%% Workflow Configuration Settings
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% Construct the Workflow Configuration Object with default settings

‎trx_examples/targeting/QPSKTxRxHDLExample/hdlworkflow_tx2.m‎

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%--------------------------------------------------------------------------
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% HDL Workflow Script
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% Generated with MATLAB 25.2 (R2025b) at 14:14:25 on 20/05/2026
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% This script was generated using the following parameter values:
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% Filename : 'C:\work\datalink\TransceiverToolbox\trx_examples\targeting\QPSKTxRxHDLExample\hdlworkflow_tx2.m'
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% Overwrite : true
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% Comments : true
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% Headers : true
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% DUT : 'commhdlQPSKTxRx/Transmitter'
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% To view changes after modifying the workflow, run the following command:
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% >> hWC.export('DUT','commhdlQPSKTxRx/Transmitter');
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%--------------------------------------------------------------------------
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%% Load the Model
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load_system('commhdlQPSKTxRx');
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%% Restore the Model to default HDL parameters
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%hdlrestoreparams('commhdlQPSKTxRx/Transmitter');
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%% Model HDL Parameters
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%% Set Model 'commhdlQPSKTxRx' HDL parameters
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hdlset_param('commhdlQPSKTxRx', 'ClockRatePipelining', 'off');
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hdlset_param('commhdlQPSKTxRx', 'HDLSubsystem', 'commhdlQPSKTxRx/Transmitter');
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hdlset_param('commhdlQPSKTxRx', 'LUTMapToRAM', 'off');
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hdlset_param('commhdlQPSKTxRx', 'ProjectFolder', 'hdl_prj_jupiter');
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hdlset_param('commhdlQPSKTxRx', 'ReferenceDesign', 'JUPITER (TX)');
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hdlset_param('commhdlQPSKTxRx', 'ReferenceDesignParameter', {'project','jupiter_sdr','ref_design','tx','preprocess','off','postprocess','off','number_of_inputs','4','number_of_bits','16','number_of_valids','1','multiple','1','HDLVerifierAXI','off','HDLVerifierFDC','JTAG'});
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hdlset_param('commhdlQPSKTxRx', 'SynthesisTool', 'Xilinx Vivado');
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hdlset_param('commhdlQPSKTxRx', 'SynthesisToolChipFamily', 'Zynq UltraScale+');
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hdlset_param('commhdlQPSKTxRx', 'SynthesisToolDeviceName', 'xczu3eg-sfva625-2-e');
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hdlset_param('commhdlQPSKTxRx', 'SynthesisToolPackageName', '');
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hdlset_param('commhdlQPSKTxRx', 'SynthesisToolSpeedValue', '');
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hdlset_param('commhdlQPSKTxRx', 'TargetDirectory', 'hdl_prj_jupiter\hdlsrc');
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hdlset_param('commhdlQPSKTxRx', 'TargetLanguage', 'Verilog');
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hdlset_param('commhdlQPSKTxRx', 'TargetPlatform', 'AnalogDevices JUPITER');
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hdlset_param('commhdlQPSKTxRx', 'Workflow', 'IP Core Generation');
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% Set SubSystem HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter', 'ProcessorFPGASynchronization', 'Free running');
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% Set Inport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/debug', 'IOInterface', 'AXI4-Lite');
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hdlset_param('commhdlQPSKTxRx/Transmitter/debug', 'IOInterfaceMapping', 'x"100"');
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% Set Inport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/dataI', 'IOInterface', 'IP Data 0 IN [0:15]');
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hdlset_param('commhdlQPSKTxRx/Transmitter/dataI', 'IOInterfaceMapping', '[0:15]');
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% Set Inport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/dataQ', 'IOInterface', 'IP Data 1 IN [0:15]');
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hdlset_param('commhdlQPSKTxRx/Transmitter/dataQ', 'IOInterfaceMapping', '[0:15]');
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% Set Inport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/validIn', 'IOInterface', 'IP Valid Tx Data IN');
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hdlset_param('commhdlQPSKTxRx/Transmitter/validIn', 'IOInterfaceMapping', '[0]');
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hdlset_param('commhdlQPSKTxRx/Transmitter/QPSK Tx/Bit Packetizer/Data Bits FIFO/No HDL', 'Architecture', 'No HDL');
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hdlset_param('commhdlQPSKTxRx/Transmitter/QPSK Tx/Bit Packetizer/Data Bits FIFO/No HDL/No HDL', 'Architecture', 'No HDL');
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% Set Outport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/dataOutI', 'IOInterface', 'ADRV9002 DAC Data I0 [0:15]');
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hdlset_param('commhdlQPSKTxRx/Transmitter/dataOutI', 'IOInterfaceMapping', '[0:15]');
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% Set Outport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/dataOutQ', 'IOInterface', 'ADRV9002 DAC Data Q0 [0:15]');
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hdlset_param('commhdlQPSKTxRx/Transmitter/dataOutQ', 'IOInterfaceMapping', '[0:15]');
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% Set Outport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/txDiagBus', 'IOInterface', 'No Interface Specified');
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hdlset_param('commhdlQPSKTxRx/Transmitter/txDiagBus', 'IOInterfaceMapping', '');
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% Set Outport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/validOut', 'IOInterface', 'IP Load Tx Data OUT');
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hdlset_param('commhdlQPSKTxRx/Transmitter/validOut', 'IOInterfaceMapping', '[0]');
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% Set Outport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/complex', 'IOInterface', 'No Interface Specified');
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hdlset_param('commhdlQPSKTxRx/Transmitter/complex', 'IOInterfaceMapping', '');
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% Set Outport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/msg_count_out', 'IOInterface', 'AXI4-Lite');
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hdlset_param('commhdlQPSKTxRx/Transmitter/msg_count_out', 'IOInterfaceMapping', 'x"104"');
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% Set Outport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/dataOutQ2', 'IOInterface', 'ADRV9002 DAC Data I1 [0:15]');
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hdlset_param('commhdlQPSKTxRx/Transmitter/dataOutQ2', 'IOInterfaceMapping', '[0:15]');
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% Set Outport HDL parameters
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hdlset_param('commhdlQPSKTxRx/Transmitter/dataOutI2', 'IOInterface', 'ADRV9002 DAC Data Q1 [0:15]');
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hdlset_param('commhdlQPSKTxRx/Transmitter/dataOutI2', 'IOInterfaceMapping', '[0:15]');
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%% Workflow Configuration Settings
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% Construct the Workflow Configuration Object with default settings
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hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx Vivado','TargetWorkflow','IP Core Generation');
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% Specify the top level project directory
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hWC.ProjectFolder = 'hdl_prj_jupiter';
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hWC.AllowUnsupportedToolVersion = true;
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hWC.ReferenceDesignToolVersion = '2025.1';
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hWC.IgnoreToolVersionMismatch = false;
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% Set Workflow tasks to run
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hWC.RunTaskGenerateRTLCodeAndIPCore = true;
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hWC.RunTaskCreateProject = true;
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hWC.RunTaskGenerateSoftwareInterface = true;
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hWC.RunTaskBuildFPGABitstream = true;
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hWC.RunTaskProgramTargetDevice = false;
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% Set properties related to 'RunTaskGenerateRTLCodeAndIPCore' Task
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hWC.GenerateIPCoreReport = true;
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% Set properties related to 'RunTaskCreateProject' Task
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hWC.Objective = hdlcoder.Objective.None;
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hWC.AdditionalProjectCreationTclFiles = '';
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hWC.EnableIPCaching = false;
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% Set properties related to 'RunTaskGenerateSoftwareInterface' Task
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hWC.GenerateSoftwareInterfaceModel = false;
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hWC.OperatingSystem = 'Linux';
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hWC.HostTargetInterface = 'Ethernet';
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hWC.GenerateHostInterfaceModel = false;
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hWC.GenerateHostInterfaceScript = false;
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% Set properties related to 'RunTaskBuildFPGABitstream' Task
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hWC.RunExternalBuild = true;
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hWC.EnableDesignCheckpoint = false;
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hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Custom;
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hWC.CustomBuildTclFile = 'C:\work\datalink\TransceiverToolbox\CI\scripts\adi_build.tcl';
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hWC.DefaultCheckpointFile = 'Default';
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hWC.RoutedDesignCheckpointFilePath = '';
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hWC.MaxNumOfCoresForBuild = '';
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% Set properties related to 'RunTaskProgramTargetDevice' Task
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% hWC.ProgrammingMethod = hdlcoder.ProgrammingMethod.Download;
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% hWC.IPAddress = '';
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% hWC.SSHUsername = '';
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% hWC.SSHPassword = '';
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% Validate the Workflow Configuration Object
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hWC.validate;
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%% Run the workflow
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hdlcoder.runWorkflow('commhdlQPSKTxRx/Transmitter', hWC, 'Verbosity', 'on');

‎trx_examples/targeting/QPSKTxRxHDLExample/rx_capture_adrv9002_hdl.mat‎

7.67 MB
Binary file not shown.

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