fixed Bug #101069 Signal widths for interface definitions not included in SV output

Author: Mikolaj Romulski

examples/ir_examples/interconnect/design.yaml

@@ -2,10 +2,6 @@ name: top
 ips:
   cpu:
     file: file:ips/cpu.yaml
-  wb_pass:
-    file: file:ips/wb_passthrough.yaml
-    parameters:
-      DW: 8
   mem:
     file: file:ips/mem.yaml
     parameters:
@@ -21,9 +17,6 @@ connections:
       rst: rst
     mem: *clkrst
     dsp: *clkrst
-  interfaces:
-    wb_pass:
-      wb_in: ext_manager
 
 interconnects:
   wishbone_bus:

topwrap/frontend/yaml/design.py

@@ -395,7 +395,7 @@ def get_refio_from_connection(
         ) -> Optional[ReferencedInterface]:
             try:
                 refio, _ = self._resolve_ref(des, name, ref)
-            except:
+            except DesignDescriptionFrontendException:
                 # skip all externals, only ModuleInstances
                 return None
             if not isinstance(refio, ReferencedInterface):

topwrap/frontend/yaml/ip_core.py

@@ -221,7 +221,10 @@ def _parse_intfs(self, desc: IPCoreDescription, mod: Module, types: dict[str, Lo
                         if isinstance(port, Port):
                             port = ReferencedPort.external(port)
 
-                        signals[byname[sname]._id] = port
+                        # we have to update definition, because by default all signals are 1bit wide
+                        ifsg = byname[sname]
+                        ifsg.type = port.io.type
+                        signals[ifsg._id] = port
                     else:
                         signals[byname[sname]._id] = None