youyeetoo r1: refactor DSI configuration into separate overlays

Split the monolithic DSI0/DSI1 configuration from rk3588s-yyt-lcd.dtsi
into two independent device tree overlays. This allows users to enable
either display without recompiling with different preprocessor defines.

Changes:
- Add youyeetoo-r1-display-dsi0.dts overlay with DSI0 panel, backlight
  (PWM12), touchscreen (i2c3), and VP2 video pipeline configuration
- Add youyeetoo-r1-display-dsi1.dts overlay with DSI1 panel, backlight1
  (PWM11), touchscreen (i2c5), and VP3 video pipeline configuration
- Remove rk3588s-yyt-lcd.dtsi and its inclusion from main dts
- Remove backlight/backlight1 and PWM11/PWM12 definitions from main dts
  as they are now integrated in respective overlays
- Update overlay/Makefile to build new overlay dtbo files

Author: SuperKali

arch/arm64/boot/dts/rockchip/overlay/Makefile

@@ -82,6 +82,8 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
 	yy3568-display-dsi1.dtbo \
 	yy3568-display-edp.dtbo \
 	yy3568-sata2.dtbo \
+	youyeetoo-r1-display-dsi0.dtbo \
+	youyeetoo-r1-display-dsi1.dtbo \
 	khadas-edge2-display-dsi0.dtbo \
 	khadas-edge2-display-dsi1.dtbo \
 	khadas-edge2-cam1.dtbo \

arch/arm64/boot/dts/rockchip/overlay/youyeetoo-r1-display-dsi0.dts

@@ -0,0 +1,222 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/display/drm_mipi_dsi.h>
+
+/*
+ * Youyeetoo R1 - RK3588S
+ * LCD DSI0 Overlay
+ */
+
+/ {
+	fragment@0 {
+		target-path = "/";
+
+		__overlay__ {
+			backlight: backlight {
+				compatible = "pwm-backlight";
+				brightness-levels = <
+					0  20  20  21  21  22  22  23
+					23  24  24  25  25  26  26  27
+					27  28  28  29  29  30  30  31
+					31  32  32  33  33  34  34  35
+					35  36  36  37  37  38  38  39
+					40  41  42  43  44  45  46  47
+					48  49  50  51  52  53  54  55
+					56  57  58  59  60  61  62  63
+					64  65  66  67  68  69  70  71
+					72  73  74  75  76  77  78  79
+					80  81  82  83  84  85  86  87
+					88  89  90  91  92  93  94  95
+					96  97  98  99 100 101 102 103
+					104 105 106 107 108 109 110 111
+					112 113 114 115 116 117 118 119
+					120 121 122 123 124 125 126 127
+					128 129 130 131 132 133 134 135
+					136 137 138 139 140 141 142 143
+					144 145 146 147 148 149 150 151
+					152 153 154 155 156 157 158 159
+					160 161 162 163 164 165 166 167
+					168 169 170 171 172 173 174 175
+					176 177 178 179 180 181 182 183
+					184 185 186 187 188 189 190 191
+					192 193 194 195 196 197 198 199
+					200 201 202 203 204 205 206 207
+					208 209 210 211 212 213 214 215
+					216 217 218 219 220 221 222 223
+					224 225 226 227 228 229 230 231
+					232 233 234 235 236 237 238 239
+					240 241 242 243 244 245 246 247
+					248 249 250 251 252 253 254 255
+				>;
+				default-brightness-level = <200>;
+				pwms = <&pwm12 0 25000 0>;
+				status = "okay";
+				power-supply = <&vcc5v0_sys>;
+			};
+		};
+	};
+
+	fragment@1 {
+		target = <&pwm12>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-names = "active";
+			pinctrl-0 = <&pwm12m1_pins>;
+		};
+	};
+
+	fragment@2 {
+		target = <&dsi0>;
+
+		__overlay__ {
+			status = "okay";
+			rockchip,lane-rate = <1000>;
+
+			dsi0_panel: panel@0 {
+				status = "okay";
+				compatible = "simple-panel-dsi";
+				reg = <0>;
+				backlight = <&backlight>;
+				reset-delay-ms = <60>;
+				enable-delay-ms = <60>;
+				prepare-delay-ms = <60>;
+				unprepare-delay-ms = <60>;
+				disable-delay-ms = <60>;
+				dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+						MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>;
+				dsi,format = <MIPI_DSI_FMT_RGB888>;
+				dsi,lanes  = <4>;
+
+				panel-init-sequence = [
+					15 00 02 80 ac
+					15 00 02 81 b8
+					15 00 02 82 09
+					15 00 02 83 78
+					15 00 02 84 7f
+					15 00 02 85 bb
+					15 00 02 86 70
+				];
+
+				panel-exit-sequence = [
+					05 00 01 28
+					05 00 01 10
+				];
+
+				disp_timings0:display-timings {
+					native-mode = <&dsi0_timing0>;
+					dsi0_timing0: timing0 {
+						clock-frequency = <51668640>;
+						hactive = <1024>;
+						vactive = <600>;
+						hfront-porch = <160>;
+						hback-porch = <160>;
+						hsync-len = <10>;
+						vfront-porch = <12>;
+						vsync-len = <10>;
+						vback-porch = <23>;
+						hsync-active = <0>;
+						vsync-active = <0>;
+						de-active = <1>;
+						pixelclk-active = <0>;
+					};
+				};
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+						panel_in_dsi: endpoint {
+							remote-endpoint = <&dsi_out_panel>;
+						};
+					};
+				};
+			};
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					reg = <1>;
+					dsi_out_panel: endpoint {
+						remote-endpoint = <&panel_in_dsi>;
+					};
+				};
+			};
+		};
+	};
+
+	fragment@3 {
+		target = <&route_dsi0>;
+
+		__overlay__ {
+			status = "okay";
+			connect = <&vp2_out_dsi0>;
+		};
+	};
+
+	fragment@4 {
+		target = <&dsi0_in_vp2>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+
+	fragment@5 {
+		target = <&dsi0_in_vp3>;
+
+		__overlay__ {
+			status = "disabled";
+		};
+	};
+
+	fragment@6 {
+		target = <&dsi0_panel>;
+
+		__overlay__ {
+			power-supply = <&vcc3v3_lcd_n>;
+			reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
+			enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&lcd_rst_gpio>;
+		};
+	};
+
+	fragment@7 {
+		target = <&i2c3>;
+
+		__overlay__ {
+			status = "okay";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c3m2_xfer>;
+
+			gt9xx: gt9xx@5d {
+				compatible = "goodix,gt9xx";
+				reg = <0x5d>;
+				touch-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+				reset-gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
+				max-x = <1024>;
+				max-y = <600>;
+				tp-size = <911>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&touch_gpio>;
+				status = "okay";
+			};
+		};
+	};
+
+	fragment@8 {
+		target = <&mipi_dcphy0>;
+
+		__overlay__ {
+			status = "okay";
+		};
+	};
+};