Fix inline code blocks formatting

daniellimws · daniellimws · commit 53731015119e · 2020-04-27T14:03:25.000+08:00
All this while it was using `code` which italicizes the code instead
of ``code``.

Signed-off-by: Daniel Lim Wee Soong &lt;weesoong.lim@gmail.com&gt;
diff --git a/tests/clocks/dff_comb_one_clock/README.rst b/tests/clocks/dff_comb_one_clock/README.rst
@@ -1,7 +1,7 @@
 D-Flipflop with combinational logic
 +++++++++++++++++++++++++++++++++++
 
-The following shows a combinational logic design driven by a clock. `input wire a` should be detected as a clock because it drives the flip flop.
+The following shows a combinational logic design driven by a clock. ``input wire a`` should be detected as a clock because it drives the flip flop.
 
 .. symbolator:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
 
@@ -16,7 +16,7 @@ The following shows a combinational logic design driven by a clock. `input wire
    :start-after:  */
    :caption: tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
 
-The `is_clock` attribute of the `a` port is set to 1, and the ports `b`, `c` and `d` have their `clock` attribute set to `a`.
+The ``is_clock`` attribute of the ``a`` port is set to 1, and the ports ``b``, ``c`` and ``d`` have their ``clock`` attribute set to ``a``.
 
 .. literalinclude:: ../../../tests/clocks/dff_comb_one_clock/golden.model.xml
    :language: xml
diff --git a/tests/clocks/dff_one_clock/README.rst b/tests/clocks/dff_one_clock/README.rst
@@ -1,23 +1,23 @@
 D-Flipflop with one clock
 +++++++++++++++++++++++++++++++++++
 
-The following shows a simple D-flip flop driven by one clock. `input wire a` should be detected as a clock because it drives the flip flop.
+The following shows a simple D-flip flop driven by one clock. ``input wire a`` should be detected as a clock because it drives the flip flop.
 
-.. symbolator:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v
+.. symbolator:: ./dff_one_clock.sim.v
 
-.. verilog-diagram:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v
+.. verilog-diagram:: ./dff_one_clock.sim.v
    :type: netlistsvg
    :module: BLOCK
 
 |
 
-.. literalinclude:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v
+.. literalinclude:: ./dff_one_clock.sim.v
    :language: verilog
    :start-after: */
    :caption: tests/clocks/dff_one_clock/dff_one_clock.sim.v
 
-As you can see in the generated model, the `is_clock` attribute of the `a` port is set to 1, while the `b` and `c` ports have their `clock` attribute set to `a`.
+As you can see in the generated model, the ``is_clock`` attribute of the ``a`` port is set to 1, while the ``b`` and ``c`` ports have their ``clock`` attribute set to ``a``.
 
-.. literalinclude:: ../../../tests/clocks/dff_one_clock/golden.model.xml
+.. literalinclude:: ./golden.model.xml
    :language: xml
    :caption: tests/clocks/dff_one_clock/golden.model.xml
diff --git a/tests/clocks/dff_two_clocks/README.rst b/tests/clocks/dff_two_clocks/README.rst
@@ -1,7 +1,7 @@
 D-Flipflop with two clocks
 +++++++++++++++++++++++++++++++++++
 
-`input wire c1` and `input wire c2` should be detected as clocks because they drive the flip flop.
+``input wire c1`` and ``input wire c2`` should be detected as clocks because they drive the flip flop.
 
 .. symbolator:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v
 
@@ -16,7 +16,7 @@ D-Flipflop with two clocks
    :start-after: */
    :caption: tests/clocks/dff_two_clocks/dff_two_clocks.sim.v
 
-The `is_clock` attribute of the `c1` and `c2` ports are set to 1, and the ports `a`, `b`, `c`, `o1` and `o2` have their `clock` attribute set to the respective clocks they are driven by.
+The ``is_clock`` attribute of the ``c1`` and ``c2`` ports are set to 1, and the ports ``a``, ``b``, ``c``, ``o1`` and ``o2`` have their ``clock`` attribute set to the respective clocks they are driven by.
 
 .. literalinclude:: ../../../tests/clocks/dff_two_clocks/golden.model.xml
    :language: xml
diff --git a/tests/clocks/input_attr_clock/README.rst b/tests/clocks/input_attr_clock/README.rst
@@ -1,7 +1,7 @@
 Manually set input as clock by setting the CLOCK attribute
 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
-The following shows that `input wire a` is given the `(* CLOCK *)` attribute.
+The following shows that ``input wire a`` is given the ``(* CLOCK *)`` attribute.
 
 .. symbolator:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v
 
@@ -12,7 +12,7 @@ The following shows that `input wire a` is given the `(* CLOCK *)` attribute.
    :start-after: */
    :caption: tests/clocks/input_attr_clock/input_attr_clock.sim.v
 
-As such, the `is_clock` attribute of the `a` port is set to 1.
+As such, the ``is_clock`` attribute of the ``a`` port is set to 1.
 
 .. literalinclude:: ../../../tests/clocks/input_attr_clock/golden.model.xml
    :language: xml
diff --git a/tests/clocks/input_attr_not_clock/README.rst b/tests/clocks/input_attr_not_clock/README.rst
@@ -1,7 +1,7 @@
 Force input as regular input by setting the CLOCK attribute
 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
-`input wire a` should be detected as a clock because it drives the flip flop. However, it has the attribute CLOCK set to 0 which should force it to be a regular input.
+``input wire a`` should be detected as a clock because it drives the flip flop. However, it has the attribute CLOCK set to 0 which should force it to be a regular input.
 
 .. symbolator:: ../../../tests/clocks/input_attr_not_clock/block.sim.v
 
@@ -16,7 +16,7 @@ Force input as regular input by setting the CLOCK attribute
    :start-after: */
    :caption: tests/clocks/input_attr_not_clock/block.sim.v
 
-As such, the `is_clock` attribute of the `a` port is not set.
+As such, the ``is_clock`` attribute of the ``a`` port is not set.
 
 .. literalinclude:: ../../../tests/clocks/input_attr_not_clock/golden.model.xml
    :language: xml
diff --git a/tests/clocks/input_named_clk/README.rst b/tests/clocks/input_named_clk/README.rst
@@ -1,7 +1,7 @@
 Set input as clock by name (clk)
 +++++++++++++++++++++++++++++++++++
 
-An input wire can be set as a clock by assigning `clk` as its name.
+An input wire can be set as a clock by assigning ``clk`` as its name.
 
 .. symbolator:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v
 
@@ -12,7 +12,7 @@ An input wire can be set as a clock by assigning `clk` as its name.
    :start-after: */
    :caption: tests/clocks/input_named_clk/input_named_clk.sim.v
 
-As such, the `is_clock` attribute of the `clk` port is set to 1, without needing to set anything else in the verilog code.
+As such, the ``is_clock`` attribute of the ``clk`` port is set to 1, without needing to set anything else in the verilog code.
 
 .. literalinclude:: ../../../tests/clocks/input_named_clk/golden.model.xml
    :language: xml
diff --git a/tests/clocks/input_named_regex/README.rst b/tests/clocks/input_named_regex/README.rst
@@ -1,7 +1,7 @@
 Set input as clock by name (regex)
 +++++++++++++++++++++++++++++++++++
 
-An input wire can be set as a clock by having `clk` in its name (case insensitive).
+An input wire can be set as a clock by having ``clk`` in its name (case insensitive).
 
 .. symbolator:: ../../../tests/clocks/input_named_regex/block.sim.v
 
@@ -12,7 +12,7 @@ An input wire can be set as a clock by having `clk` in its name (case insensitiv
    :start-after: */
    :caption: tests/clocks/input_named_regex/block.sim.v
 
-As such, the `is_clock` attribute of wires with a variation of `clk` in their name is set to 1.
+As such, the ``is_clock`` attribute of wires with a variation of ``clk`` in their name is set to 1.
 
 .. literalinclude:: ../../../tests/clocks/input_named_regex/golden.model.xml
    :language: xml
diff --git a/tests/clocks/multiple_inputs_named_clk/README.rst b/tests/clocks/multiple_inputs_named_clk/README.rst
@@ -1,7 +1,7 @@
 Set inputs as clock by name (multiple clock inputs)
 +++++++++++++++++++++++++++++++++++++++++++++++++++
 
-`input wire rdclk` and `input wire wrclk` have `clk` in their names, hence are recognized as clock inputs by v2x.
+``input wire rdclk`` and ``input wire wrclk`` have ``clk`` in their names, hence are recognized as clock inputs by v2x.
 
 .. symbolator:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
 
@@ -12,7 +12,7 @@ Set inputs as clock by name (multiple clock inputs)
    :start-after: */
    :caption: tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
 
-As such, the `is_clock` attribute of the `rdclk` and `wrclk` ports are set to 1.
+As such, the ``is_clock`` attribute of the ``rdclk`` and ``wrclk`` ports are set to 1.
 
 .. literalinclude:: ../../../tests/clocks/multiple_inputs_named_clk/golden.model.xml
    :language: xml
diff --git a/tests/clocks/multiple_outputs_named_clk/README.rst b/tests/clocks/multiple_outputs_named_clk/README.rst
@@ -1,7 +1,7 @@
 Set outputs as clock by name (multiple clock outputs)
 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
-`output wire rdclk` and `output wire wrclk` have `clk` in their names, hence are recognized as clock inputs by v2x.
+``output wire rdclk`` and ``output wire wrclk`` have ``clk`` in their names, hence are recognized as clock inputs by v2x.
 
 .. symbolator:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
 
@@ -12,7 +12,7 @@ Set outputs as clock by name (multiple clock outputs)
    :start-after: */
    :caption: tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
 
-As such, the `is_clock` attribute of the `rdclk` and `wrclk` ports are set to 1.
+As such, the ``is_clock`` attribute of the ``rdclk`` and ``wrclk`` ports are set to 1.
 
 .. literalinclude:: ../../../tests/clocks/multiple_outputs_named_clk/golden.model.xml
    :language: xml
diff --git a/tests/clocks/output_attr_clock/README.rst b/tests/clocks/output_attr_clock/README.rst
@@ -1,7 +1,7 @@
 Manually set output as clock by setting the CLOCK attribute
 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
-The following shows that `output wire o` is given the `(* CLOCK *)` attribute.
+The following shows that ``output wire o`` is given the ``(* CLOCK *)`` attribute.
 
 .. symbolator:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v
 
@@ -12,7 +12,7 @@ The following shows that `output wire o` is given the `(* CLOCK *)` attribute.
    :start-after: */
    :caption: tests/clocks/output_attr_clock/output_attr_clock.sim.v
 
-As such, the `is_clock` attribute of the `o` port is set to 1.
+As such, the ``is_clock`` attribute of the ``o`` port is set to 1.
 
 .. literalinclude:: ../../../tests/clocks/output_attr_clock/golden.model.xml
    :language: xml
diff --git a/tests/clocks/output_named_clk/README.rst b/tests/clocks/output_named_clk/README.rst
@@ -1,7 +1,7 @@
 Set output as clock by name (clk)
 +++++++++++++++++++++++++++++++++++
 
-An output wire can be set as a clock by assigning `clk` as its name.
+An output wire can be set as a clock by assigning ``clk`` as its name.
 
 .. symbolator:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v
 
@@ -12,7 +12,7 @@ An output wire can be set as a clock by assigning `clk` as its name.
    :start-after: */
    :caption: tests/clocks/output_named_clk/output_named_clk.sim.v
 
-As such, the `is_clock` attribute of the `clk` output port is set to 1.
+As such, the ``is_clock`` attribute of the ``clk`` output port is set to 1.
 
 .. literalinclude:: ../../../tests/clocks/output_named_clk/golden.model.xml
    :language: xml
