Remove netlistsvg diagram for blackbox modules and add pb_type.xml

Signed-off-by: Daniel Lim Wee Soong <weesoong.lim@gmail.com>

Author: daniellimws

tests/clocks/dff_comb_one_clock/README.rst

@@ -8,13 +8,16 @@ The following shows a combinational logic design driven by a clock. `input wire
 .. verilog-diagram:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
    :type: netlistsvg
    :module: BLOCK
-   :caption: tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
+
+|
 
 .. literalinclude:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
    :language: verilog
    :start-after:  */
+   :caption: tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
 
 The `is_clock` attribute of the `a` port is set to 1, and the ports `b`, `c` and `d` have their `clock` attribute set to `a`.
 
 .. literalinclude:: ../../../tests/clocks/dff_comb_one_clock/golden.model.xml
-   :language: xml
+   :language: xml
+   :caption: tests/clocks/dff_comb_one_clock/golden.model.xml

tests/clocks/dff_one_clock/README.rst

@@ -8,13 +8,16 @@ The following shows a simple D-flip flop driven by one clock. `input wire a` sho
 .. verilog-diagram:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v
    :type: netlistsvg
    :module: BLOCK
-   :caption: tests/clocks/dff_one_clock/dff_one_clock.sim.v
+
+|
 
 .. literalinclude:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v
    :language: verilog
    :start-after: */
+   :caption: tests/clocks/dff_one_clock/dff_one_clock.sim.v
 
 As you can see in the generated model, the `is_clock` attribute of the `a` port is set to 1, while the `b` and `c` ports have their `clock` attribute set to `a`.
 
 .. literalinclude:: ../../../tests/clocks/dff_one_clock/golden.model.xml
    :language: xml
+   :caption: tests/clocks/dff_one_clock/golden.model.xml

tests/clocks/dff_two_clocks/README.rst

@@ -8,13 +8,16 @@ D-Flipflop with two clocks
 .. verilog-diagram:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v
    :type: netlistsvg
    :module: BLOCK
-   :caption: tests/clocks/dff_two_clocks/dff_two_clocks.sim.v
+
+|
 
 .. literalinclude:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v
    :language: verilog
    :start-after: */
+   :caption: tests/clocks/dff_two_clocks/dff_two_clocks.sim.v
 
 The `is_clock` attribute of the `c1` and `c2` ports are set to 1, and the ports `a`, `b`, `c`, `o1` and `o2` have their `clock` attribute set to the respective clocks they are driven by.
 
 .. literalinclude:: ../../../tests/clocks/dff_two_clocks/golden.model.xml
    :language: xml
+   :caption: tests/clocks/dff_two_clocks/golden.model.xml

tests/clocks/input_attr_clock/README.rst

@@ -5,16 +5,15 @@ The following shows that `input wire a` is given the `(* CLOCK *)` attribute.
 
 .. symbolator:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v
 
-.. verilog-diagram:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v
-   :type: netlistsvg
-   :module: BLOCK
-   :caption: tests/clocks/input_attr_clock/input_attr_clock.sim.v
+|
 
 .. literalinclude:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v
    :language: verilog
    :start-after: */
+   :caption: tests/clocks/input_attr_clock/input_attr_clock.sim.v
 
 As such, the `is_clock` attribute of the `a` port is set to 1.
 
 .. literalinclude:: ../../../tests/clocks/input_attr_clock/golden.model.xml
-   :language: xml
+   :language: xml
+   :caption: tests/clocks/input_attr_clock/golden.model.xml

tests/clocks/input_attr_not_clock/README.rst

@@ -8,13 +8,20 @@ Force input as regular input by setting the CLOCK attribute
 .. verilog-diagram:: ../../../tests/clocks/input_attr_not_clock/block.sim.v
    :type: netlistsvg
    :module: BLOCK
-   :caption: tests/clocks/input_attr_not_clock/block.sim.v
+
+|
 
 .. literalinclude:: ../../../tests/clocks/input_attr_not_clock/block.sim.v
    :language: verilog
    :start-after: */
+   :caption: tests/clocks/input_attr_not_clock/block.sim.v
 
 As such, the `is_clock` attribute of the `a` port is not set.
 
 .. literalinclude:: ../../../tests/clocks/input_attr_not_clock/golden.model.xml
-   :language: xml
+   :language: xml
+   :caption: tests/clocks/input_attr_not_clock/golden.model.xml
+
+.. literalinclude:: ../../../tests/clocks/input_attr_not_clock/golden.pb_type.xml
+   :language: xml
+   :caption: tests/clocks/input_attr_not_clock/golden.pb_type.xml

tests/clocks/input_named_clk/README.rst

@@ -5,16 +5,15 @@ An input wire can be set as a clock by assigning `clk` as its name.
 
 .. symbolator:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v
 
-.. verilog-diagram:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v
-   :type: netlistsvg
-   :module: BLOCK
-   :caption: tests/clocks/input_named_clk/input_named_clk.sim.v
+|
 
 .. literalinclude:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v
    :language: verilog
    :start-after: */
+   :caption: tests/clocks/input_named_clk/input_named_clk.sim.v
 
 As such, the `is_clock` attribute of the `clk` port is set to 1, without needing to set anything else in the verilog code.
 
 .. literalinclude:: ../../../tests/clocks/input_named_clk/golden.model.xml
-   :language: xml
+   :language: xml
+   :caption: tests/clocks/input_named_clk/golden.model.xml

tests/clocks/input_named_regex/README.rst

@@ -5,16 +5,19 @@ An input wire can be set as a clock by having `clk` in its name (case insensitiv
 
 .. symbolator:: ../../../tests/clocks/input_named_regex/block.sim.v
 
-.. verilog-diagram:: ../../../tests/clocks/input_named_regex/block.sim.v
-   :type: netlistsvg
-   :module: BLOCK
-   :caption: tests/clocks/input_named_regex/block.sim.v
+|
 
 .. literalinclude:: ../../../tests/clocks/input_named_regex/block.sim.v
    :language: verilog
    :start-after: */
+   :caption: tests/clocks/input_named_regex/block.sim.v
 
 As such, the `is_clock` attribute of wires with a variation of `clk` in their name is set to 1.
 
 .. literalinclude:: ../../../tests/clocks/input_named_regex/golden.model.xml
-   :language: xml
+   :language: xml
+   :caption: tests/clocks/input_named_regex/golden.model.xml
+
+.. literalinclude:: ../../../tests/clocks/input_named_regex/golden.pb_type.xml
+   :language: xml
+   :caption: tests/clocks/input_named_regex/golden.pb_type.xml

tests/clocks/multiple_inputs_named_clk/README.rst

@@ -5,16 +5,15 @@ Set inputs as clock by name (multiple clock inputs)
 
 .. symbolator:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
 
-.. verilog-diagram:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
-   :type: netlistsvg
-   :module: BLOCK
-   :caption: tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
+|
 
 .. literalinclude:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
    :language: verilog
    :start-after: */
+   :caption: tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
 
 As such, the `is_clock` attribute of the `rdclk` and `wrclk` ports are set to 1.
 
 .. literalinclude:: ../../../tests/clocks/multiple_inputs_named_clk/golden.model.xml
-   :language: xml
+   :language: xml
+   :caption: tests/clocks/multiple_inputs_named_clk/golden.model.xml

tests/clocks/multiple_outputs_named_clk/README.rst

@@ -5,16 +5,15 @@ Set outputs as clock by name (multiple clock outputs)
 
 .. symbolator:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
 
-.. verilog-diagram:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
-   :type: netlistsvg
-   :module: BLOCK
-   :caption: tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
+|
 
 .. literalinclude:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
    :language: verilog
    :start-after: */
+   :caption: tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
 
 As such, the `is_clock` attribute of the `rdclk` and `wrclk` ports are set to 1.
 
 .. literalinclude:: ../../../tests/clocks/multiple_outputs_named_clk/golden.model.xml
-   :language: xml
+   :language: xml
+   :caption: tests/clocks/multiple_outputs_named_clk/golden.model.xml

tests/clocks/output_attr_clock/README.rst

@@ -5,16 +5,15 @@ The following shows that `output wire o` is given the `(* CLOCK *)` attribute.
 
 .. symbolator:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v
 
-.. verilog-diagram:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v
-   :type: netlistsvg
-   :module: BLOCK
-   :caption: tests/clocks/output_attr_clock/output_attr_clock.sim.v
+|
 
 .. literalinclude:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v
    :language: verilog
    :start-after: */
+   :caption: tests/clocks/output_attr_clock/output_attr_clock.sim.v
 
 As such, the `is_clock` attribute of the `o` port is set to 1.
 
 .. literalinclude:: ../../../tests/clocks/output_attr_clock/golden.model.xml
-   :language: xml
+   :language: xml
+   :caption: tests/clocks/output_attr_clock/golden.model.xml