sail.json

{
  "$schema": "/opt/riscv/share/sail-riscv/sail_riscv_config_schema.json",
  "base": {
    "xlen": 64,
    "E": false,
    "writable_misa": false,
    "writable_fiom": true,
    "writable_hpm_counters": {
      "len": 32,
      "value": "0xFFFF_FFFF"
    },
    // These settings control whether the specified exceptions
    // cause information to be written into the appropriate
    // `xtval` registers.
    "xtval_nonzero": {
      "illegal_instruction": true,
      "software_breakpoint": true,
      "hardware_breakpoint": true,
      "load_address_misaligned": true,
      "load_access_fault": true,
      "load_page_fault": true,
      "samo_address_misaligned": true,
      "samo_access_fault": true,
      "samo_page_fault": true,
      "fetch_address_misaligned": true,
      "fetch_access_fault": true,
      "fetch_page_fault": true,
      "software_check": true,
      "reserved_exceptions": false
    },
    "reserved_behavior": {
      // The configuration option determines how to handle the reserved behavior `amocas_odd_registers`.
      // "AMOCAS_Fatal"  – raise a Sail exception, stopping execution.
      // "AMOCAS_Illegal" – treat it as an illegal instruction.
      "amocas_odd_register": "AMOCAS_Illegal",
      // The configuration option determines how to handle execution of a floating-point
      // instruction with DYN (dynamic) rounding mode when `fcsr.FRM` contains a
      // reserved value (0b101, 0b110, 0b111).
      // This does not affect the execution of floating-point instructions that have a
      // reserved rounding mode statically encoded in the instruction.
      // "Fcsr_RM_Fatal"  – raise a Sail exception, stopping execution.
      // "Fcsr_RM_Illegal" – treat it as an illegal instruction.
      "fcsr_rm": "Fcsr_RM_Illegal",
      // The configuration option determines how to handle the reserved behavior `pmpcfg_with_R0W1`.
      // "PMP_Fatal"  – raise a Sail exception, stopping execution.
      // "PMP_ClearPermissions" – convert a PMP entry with R=0, W=1 to R=0, W=0, X=0.
      "pmpcfg_write_only": "PMP_ClearPermissions",
      // The configuration option determines how to handle the reserved behavior `xenvcfg.CBIE` with 0b10.
      // "Xenvcfg_Fatal"  – raise a Sail exception, stopping execution.
      // "Xenvcfg_ClearPermissions" – convert CBIE with 0b10 to 0b00.
      "xenvcfg_cbie": "Xenvcfg_ClearPermissions",
      // The configuration option determines how to handle the reserved behavior: Odd-numbered registers for RV32Zdinx.
      // "Zdinx_Fatal"  – raise a Sail exception, stopping execution.
      // "Zdinx_Illegal" – treat it as an illegal instruction.
      "rv32zdinx_odd_register": "Zdinx_Illegal"
    }
  },
  "memory": {
    "pmp": {
      "grain": 4,
      // This specifies the number of PMP entries present.
      // The value must be one of 0, 16, or 64.
      "count": 16,
      // This specifies the number of usable PMP entries.
      // Entries higher than this are read-only-zero.
      // The value must be less than or equal to `count`.
      "usable_count": 16,
      "tor_supported": true,
      "na4_supported": false,
      "napot_supported": true
    },
    // This controls global support for misaligned access so it is
    // checked before address translation. `misaligned_fault` in
    // `regions` is checked after address translation.
    "misaligned": {
      "supported": true,
      "byte_by_byte": false,
      "order_decreasing": false,
      "allowed_within_exp": 0
    },
    "translation": {
      "dirty_update": false
    },
    // Address to write DTB to (if provided).
    "dtb_address": {
      "len": 64,
      "value": "0x1000"
    },
    "regions": [
      // ROM
      {
        "base": {
          "len": 64,
          "value": "0x1000"
        },
        "size": {
          "len": 64,
          "value": "0x1000"
        },
        "attributes": {
          "cacheable": true,
          "coherent": true,
          "executable": false,
          "readable": true,
          "writable": false,
          "read_idempotent": true,
          "write_idempotent": true,
          "misaligned_fault": "NoFault",
          "reservability": "RsrvNone",
          "supports_cbo_zero": false
        },
        "include_in_device_tree": false
      },
      // MMIO
      {
        "base": {
          "len": 64,
          "value": "0x2000000"
        },
        "size": {
          "len": 64,
          "value": "0x2000000"
        },
        "attributes": {
          "cacheable": false,
          "coherent": true,
          "executable": false,
          "readable": true,
          "writable": true,
          "read_idempotent": false,
          "write_idempotent": false,
          "misaligned_fault": "AlignmentFault",
          "reservability": "RsrvNone",
          "supports_cbo_zero": false
        },
        "include_in_device_tree": false
      },
      // RAM
      {
        "base": {
          "len": 64,
          "value": "0x80000000"
        },
        "size": {
          "len": 64,
          "value": "0x80000000"
        },
        "attributes": {
          "cacheable": true,
          "coherent": true,
          "executable": true,
          "readable": true,
          "writable": true,
          "read_idempotent": true,
          "write_idempotent": true,
          "misaligned_fault": "NoFault",
          "reservability": "RsrvEventual",
          "supports_cbo_zero": true
        },
        "include_in_device_tree": true
      }
    ]
  },
  "platform": {
    "vendorid": 1538,
    "archid": 36,
    "impid": 256,
    "hartid": 0,
    // Cache block size, specified as a power of 2.
    "cache_block_size_exp": 6,
    // This specifies both the size and alignment of the reservation set, specified as a power of 2.
    // It must be at least 2 on RV32 and 3 on RV64 to support Zalrsc.  It must not be more than
    // 6 for Za64rs and 7 for Za128rs.  In all cases, it must be less than or equal to 12.
    "reservation_set_size_exp": 3,
    "clint": {
      // This must be in a suitable memory region (see `memory.regions`).
      "base": 33554432,
      "size": 786432
    },
    "clock_frequency": 1000000000,
    "instructions_per_tick": 2,
    "wfi_is_nop": true
  },
  "extensions": {
    "M": {
      "supported": true
    },
    "A": {
      "supported": true
    },
    "F": {
      "supported": true
    },
    "D": {
      "supported": true
    },
    "V": {
      // `support_level` must be one of the below strings:
      // . "Disabled" for no vector extension support
      // . "Integer" for Zve*x support
      // . "Float_single" for Zve*f support
      // . "Float_double" for Zve*d support
      // . "Full" for the full V extension
      // Note that `support_level` requires compatible
      // values for `vlen_exp` and `elen_exp` below.
      // For e.g. Zve32x and Zve32f require `elen_exp` >= 5,
      // Zve64x, Zve64f, and Zve64d require `elen_exp` >= 6,
      // and V requires `elen_exp` >= 6 and `vlen_exp` >= 7.
      "support_level": "Disabled",
      "vlen_exp": 8,
      "elen_exp": 6,
      "vl_use_ceil": false
    },
    "B": {
      "supported": true
    },
    "S": {
      "supported": true
    },
    "U": {
      "supported": true
    },
    "Zibi": {
      "supported": false
    },
    "Zicbom": {
      "supported": true
    },
    "Zicbop": {
      "supported": true
    },
    "Zicboz": {
      "supported": true
    },
    // This extension just asserts that the cache block size is 64 bytes.
    // If you enable this you also need to ensure `platform.cache_block_size_exp`
    // is 6, otherwise you will get a config validation error.
    "Zic64b": {
      "supported": true
    },
    "Zicfilp": {
      "supported": false
    },
    "Zicond": {
      "supported": true
    },
    "Zicntr": {
      "supported": true
    },
    "Zicsr": {
      "supported": true
    },
    "Zifencei": {
      "supported": true
    },
    "Zihintntl": {
      "supported": true
    },
    "Zihintpause": {
      "supported": true
    },
    "Zihpm": {
      "supported": true
    },
    "Zimop": {
      "supported": false
    },
    "Zmmul": {
      "supported": false
    },
    "Zaamo": {
      "supported": false
    },
    "Zabha": {
      "supported": false
    },
    "Zacas": {
      "supported": false
    },
    "Zalrsc": {
      "supported": false
    },
    "Zawrs": {
      "supported": false,
      "nto": {
        "is_nop": false
      },
      "sto": {
        "is_nop": false
      }
    },
    "Zfa": {
      "supported": true
    },
    "Zfbfmin": {
      "supported": false
    },
    "Zfh": {
      "supported": true
    },
    "Zfhmin": {
      "supported": false
    },
    "Zfinx": {
      "supported": false
    },
    "Zdinx": {
      "supported": false
    },
    "Zca": {
      "supported": true
    },
    "Zcf": {
      "supported": false
    },
    "Zcd": {
      "supported": true
    },
    "Zcb": {
      "supported": true
    },
    "Zcmop": {
      "supported": false
    },
    "Zba": {
      "supported": false
    },
    "Zbb": {
      "supported": false
    },
    "Zbs": {
      "supported": false
    },
    "Zbc": {
      "supported": true
    },
    "Zbkb": {
      "supported": true
    },
    "Zbkc": {
      "supported": true
    },
    "Zbkx": {
      "supported": true
    },
    "Zknd": {
      "supported": true
    },
    "Zkne": {
      "supported": true
    },
    "Zknh": {
      "supported": true
    },
    "Zkr": {
      "supported": false,
      "sseed_reset_value": false,
      "useed_reset_value": false,
      "sseed_read_only_zero": false,
      "useed_read_only_zero": false
    },
    "Zksed": {
      "supported": false
    },
    "Zksh": {
      "supported": false
    },
    "Zkt": {
      "supported": true
    },
    "Zhinx": {
      "supported": false
    },
    "Zhinxmin": {
      "supported": false
    },
    "Zvabd": {
      "supported": false
    },
    "Zvfbfmin": {
      "supported": false
    },
    "Zvfbfwma": {
      "supported": false
    },
    "Zvfh": {
      "supported": false
    },
    "Zvfhmin": {
      "supported": false
    },
    "Zvbb": {
      "supported": false
    },
    "Zvbc": {
      "supported": false
    },
    "Zvkb": {
      "supported": false
    },
    "Zvkg": {
      "supported": false
    },
    "Zvkned": {
      "supported": false
    },
    "Zvknha": {
      "supported": false
    },
    "Zvknhb": {
      "supported": false
    },
    "Zvksed": {
      "supported": false
    },
    "Zvksh": {
      "supported": false
    },
    "Zvkt": {
      "supported": false
    },
    "Sscofpmf": {
      "supported": false
    },
    "Sstc": {
      "supported": true
    },
    // Enabling Sstvala requires that the exceptions specified in the extension
    // have their appropriate settings under `base.xtval_nonzero`.
    "Sstvala": {
      "supported": true
    },
    "Svinval": {
      "supported": true
    },
    "Svrsw60t59b": {
      "supported": false
    },
    "Smcntrpmf": {
      "supported": false
    },
    "Svbare": {
      "supported": true,
      "sfence_vma_illegal_if_svbare_only": true
    },
    "Sv32": {
      "supported": false
    },
    "Sv39": {
      "supported": true
    },
    "Sv48": {
      "supported": true
    },
    "Sv57": {
      "supported": true
    },
    "Stateen": {
      "Smstateen": {
        "supported": false
      },
      "Ssstateen": {
        "supported": false
      },
      "C_readonly_zero": true,
      "SE0_readonly_zero": false
    },
    "Ssqosid": {
      "supported": false,
      "rcid_length": 12,
      "mcid_length": 12
    }
  }
}