Merge branch 'act4' into fix/dry-run-and-build-plan-fixes

Author: Aditya Amol Kuchekar

coverpoints/coverage/RISCV_instruction_sample.svh

@@ -5952,7 +5952,7 @@
             ins.add_rs2(2);
         end
         "amocas.d"     : begin
-            ins.add_rd(0);
+            ins.add_rd_pair(0);
             ins.add_rs2(1);
             ins.add_rs1(2);
         end
@@ -6101,7 +6101,7 @@
             ins.add_rs1(2);
         end
         "amocas.q"     : begin
-            ins.add_rd(0);
+            ins.add_rd_pair(0);
             ins.add_rs2(1);
             ins.add_rs1(2);
         end

coverpoints/norm/Zacas.yaml

@@ -3,40 +3,55 @@
 
 normative_rule_definitions:
   - name: Zacas_rv32_amocas-w_op
-    coverpoint: [""]
+    coverpoint:
+      [
+        "Zacas_amocas_w_cg/{cp_asm_count, cp_rs1, cp_rs2, cp_rd, cmp_rd_rs1_val_eq, cmp_rd_rs1_val_lsb, cmp_rd_rs1_val_hw}",
+      ]
 
   - name: Zacas_rv32_amocas-d_op
-    coverpoint: [""]
+    coverpoint:
+      [
+        "Zacas_amocas_d_cg/{cp_asm_count, cp_rs1, cp_rs2, cp_rd, cmp_rd_rs1_val_eq, cmp_rd_rs1_val_lsb, cmp_rd_rs1_val_hw, cmp_rd_rs1_val_w, cmp_rd_rs1_pair_partial_val}",
+      ]
 
   - name: Zacas_rv32_amocas-d_frst_pair_entry_reg_even
-    coverpoint: [""]
+    coverpoint: ["Zacas_amocas_d_cg/{cp_rs2_pair, cp_rd_pair}"]
 
   - name: Zacas_rv32_amocas-d_rs2_frst_reg_x0
-    coverpoint: [""]
+    coverpoint: ["Zacas_amocas_d_cg/{cp_rs2}"]
 
   - name: Zacas_rv32_amocas-d_rd_frst_reg_x0
-    coverpoint: [""]
+    coverpoint: ["Zacas_amocas_d_cg/{cp_rd}"]
 
   - name: Zacas_rv64_amocas-w_op
-    coverpoint: [""]
+    coverpoint:
+      [
+        "Zacas_amocas_w_cg/{cp_asm_count, cp_rs1, cp_rs2, cp_rd, cmp_rd_rs1_val_eq, cmp_rd_rs1_val_lsb, cmp_rd_rs1_val_hw, cmp_rd_sign_ext}",
+      ]
 
   - name: Zacas_rv64_amocas-d_op
-    coverpoint: [""]
+    coverpoint:
+      [
+        "Zacas_amocas_d_cg/{cp_asm_count, cp_rs1, cp_rs2, cp_rd, cmp_rd_rs1_val_eq, cmp_rd_rs1_val_lsb, cmp_rd_rs1_val_hw, cmp_rd_rs1_val_w}",
+      ]
 
   - name: Zacas_rv64_amocas-q_op
-    coverpoint: [""]
+    coverpoint:
+      [
+        "Zacas_amocas_q_cg/{cp_asm_count, cp_rs1, cp_rs2, cp_rd, cmp_rd_rs1_val_eq, cmp_rd_rs1_val_lsb, cmp_rd_rs1_val_hw, cmp_rd_rs1_val_w, cmp_rd_rs1_pair_partial_val}",
+      ]
 
   - name: Zacas_rv64_amocas-q_frst_pair_entry_reg_even
-    coverpoint: [""]
+    coverpoint: ["Zacas_amocas_q_cg/{cp_rs2_pair, cp_rd_pair}"]
 
   - name: Zacas_rv64_amocas-q_rs2_frst_reg_x0
-    coverpoint: [""]
+    coverpoint: ["Zacas_amocas_q_cg/{cp_rs2}"]
 
   - name: Zacas_rv64_amocas-q_rd_frst_reg_x0
-    coverpoint: [""]
+    coverpoint: ["Zacas_amocas_q_cg/{cp_rd}"]
 
   - name: Zacas_amocas_rs1_addr_alignment
-    coverpoint: [""]
+    coverpoint: ["ExceptionsZaamo_cg/{cp_amo_address_misaligned}"]
 
   - name: Zacas_amocas_mem_op_success_aq_rl
     coverpoint: [""]

coverpoints/norm/Zimop.yaml

@@ -2,13 +2,12 @@
 
 normative_rule_definitions:
   - name: mop_r_op
-    # mop.r.n writes the value zero to rd. rs1 is ignored architecturally.
-    coverpoint: ["Zimop_mop_r_cg/{cp_asm_count, cp_rs1, cp_rd, cp_rs1_edges}"]
+    coverpoint:
+      ["Zimop_mop_r_cg/{cp_asm_count, cp_rs1, cp_rd, cp_rs1_edges, cmp_rd_rs1}"]
   - name: mop_rr_op
-    # mop.rr.n writes the value zero to rd. rs1 and rs2 are ignored architecturally.
     coverpoint:
       [
-        "Zimop_mop_rr_cg/{cp_asm_count, cp_rs1, cp_rs2, cp_rd, cp_rs1_edges, cp_rs2_edges, cr_rs1_rs2_edges}",
+        "Zimop_mop_rr_cg/{cp_asm_count, cp_rs1, cp_rs2, cp_rd, cp_rs1_edges, cp_rs2_edges, cmp_rd_rs1, cmp_rd_rs2, cmp_rd_rs1_rs2}",
       ]
 
   - name: Zimop_mop-r_enc

coverpoints/priv/ExceptionsZaamo_coverage.svh

@@ -25,6 +25,8 @@ covergroup ExceptionsZaamo_cg with function sample(ins_t ins);
         wildcard bins amomaxu_w = {AMOMAXU_W};
         wildcard bins amomin_w  = {AMOMIN_W};
         wildcard bins amominu_w = {AMOMINU_W};
+        wildcard bins amocas_w  = {AMOCAS_W};
+        wildcard bins amocas_d  = {AMOCAS_D};
         `ifdef UDB_MXLEN_64
             wildcard bins amoswap_d = {AMOSWAP_D};
             wildcard bins amoadd_d  = {AMOADD_D};
@@ -35,6 +37,7 @@ covergroup ExceptionsZaamo_cg with function sample(ins_t ins);
             wildcard bins amomaxu_d = {AMOMAXU_D};
             wildcard bins amomin_d  = {AMOMIN_D};
             wildcard bins amominu_d = {AMOMINU_D};
+            wildcard bins amocas_q  = {AMOCAS_Q};
         `endif
         `ifdef ZABHA_SUPPORTED
             wildcard bins amoswap_h = {AMOSWAP_H};

coverpoints/unpriv/Zacas_coverage.svh

@@ -24,10 +24,32 @@ covergroup Zacas_amocas_w_cg with function sample(ins_t ins);
         ignore_bins x0 = {x0};
     }
 
+cmp_rd_rs1_val_eq : coverpoint (ins.current.rd_val == ins.prev.rd_val) iff (ins.trap == 0) {
+    // Compare rd current to rd previous value (which is the same as rs1 value for the current instruction)
+}
+
+    cmp_rd_rs1_val_hw : coverpoint (ins.current.rd_val[15:0] == ins.prev.rd_val[15:0]) iff (ins.trap == 0) {
+        // Compare the lowest 16 bits of current rd value to
+        // lowest 16 bits of previous rd value (which is the same as rs1 value for the current instruction)
+        bins rd_equal_val_hw_rs1  = {1}; // Cases where the lowest 16 bits of rd and rs1 are equal
+        bins rd_not_equal_val_hw_rs1  = {0}; // Cases where the lowest 16 bits of rd and rs1 are not equal
+    }
+
+    cmp_rd_rs1_val_lsb : coverpoint (ins.current.rd_val[7:0] == ins.prev.rd_val[7:0]) iff (ins.trap == 0) {
+        // Compare the least significant byte of current rd value to the
+        // least significant byte of previous rd value (which is the same as rs1 value for the current instruction)
+        bins rd_equal_val_lsb_rs1  = {1};  // Cases where the least significant byte of rd and rs1 are equal
+        bins rd_not_equal_val_lsb_rs1  = {0};  // Cases where the least significant byte of rd and rs1 are not equal
+    }
+
     cmp_rd_rs2 : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.current.rd == ins.current.rs2 & ins.trap == 0 )  {
         // Compare assignments of all registers
     }
 
+    cmp_rd_sign_ext : coverpoint ins.current.rd_val[31] iff (ins.trap == 0) {
+
+    }
+
     cmp_rs1_rs2_nx0 : coverpoint ins.get_gpr_reg(ins.current.rs1)  iff (ins.current.rs1 == ins.current.rs2 & ins.trap == 0 )  {
         // Compare assignments of all 31 registers excluding x0
         ignore_bins x0 = {x0};
@@ -99,12 +121,47 @@ covergroup Zacas_amocas_d_cg with function sample(ins_t ins);
         bins reg_pair[] = {[$:$]} with (item % 2 == 0);
     }
 
+    cmp_rd_rs1_pair_partial_val : coverpoint (
+            (ins.current.rd_val == ins.prev.rd_val) ^
+            (ins.current.rd_next_val == ins.prev.rd_next_val)
+        ) iff (ins.trap == 0)
+        {
+        // Cases where rd and rs1 have matching high or low halves but not both
+            bins rd_pair_partial_equal_val_rs1 = {1};
+            bins rd_pair_partial_not_equal_val_rs1 = {0};
+        }
+
     cmp_rd_rs1_rs2_nx0_pair : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.current.rd == ins.current.rs1 & ins.current.rd == ins.current.rs2 & ins.trap == 0 )  {
         // Compare assignments of all even registers excluding x0
         ignore_bins x0 = {x0};
         bins reg_pair[] = {[$:$]} with (item % 2 == 0);
     }
 
+cmp_rd_rs1_val_eq : coverpoint (ins.current.rd_val == ins.prev.rd_val) iff (ins.trap == 0) {
+    // Compare rd current to rd previous value (which is the same as rs1 value for the current instruction)
+}
+
+    cmp_rd_rs1_val_hw : coverpoint (ins.current.rd_val[15:0] == ins.prev.rd_val[15:0]) iff (ins.trap == 0) {
+        // Compare the lowest 16 bits of current rd value to
+        // lowest 16 bits of previous rd value (which is the same as rs1 value for the current instruction)
+        bins rd_equal_val_hw_rs1  = {1}; // Cases where the lowest 16 bits of rd and rs1 are equal
+        bins rd_not_equal_val_hw_rs1  = {0}; // Cases where the lowest 16 bits of rd and rs1 are not equal
+    }
+
+    cmp_rd_rs1_val_lsb : coverpoint (ins.current.rd_val[7:0] == ins.prev.rd_val[7:0]) iff (ins.trap == 0) {
+        // Compare the least significant byte of current rd value to the
+        // least significant byte of previous rd value (which is the same as rs1 value for the current instruction)
+        bins rd_equal_val_lsb_rs1  = {1};  // Cases where the least significant byte of rd and rs1 are equal
+        bins rd_not_equal_val_lsb_rs1  = {0};  // Cases where the least significant byte of rd and rs1 are not equal
+    }
+
+    cmp_rd_rs1_val_w : coverpoint (ins.current.rd_val[31:0] == ins.prev.rd_val[31:0]) iff (ins.trap == 0) {
+        // Compare the lowest 32 bits of current rd value to the
+        // lowest 32 bits of previous rd value (which is the same as rs1 value for the current instruction)
+        bins rd_equal_val_w_rs1  = {1}; // Cases where the lowest 32 bits of rd and rs1 are equal
+        bins rd_not_equal_val_w_rs1  = {0}; // Cases where the lowest 32 bits of rd and rs1 are not equal
+    }
+
     cmp_rd_rs2_pair : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.current.rd == ins.current.rs2 & ins.trap == 0 )  {
         // Compare assignments of all even registers
         bins reg_pair[] = {[$:$]} with (item % 2 == 0);
@@ -186,6 +243,31 @@ covergroup Zacas_amocas_d_cg with function sample(ins_t ins);
         ignore_bins x0 = {x0};
     }
 
+cmp_rd_rs1_val_eq : coverpoint (ins.current.rd_val == ins.prev.rd_val) iff (ins.trap == 0) {
+    // Compare rd current to rd previous value (which is the same as rs1 value for the current instruction)
+}
+
+    cmp_rd_rs1_val_hw : coverpoint (ins.current.rd_val[15:0] == ins.prev.rd_val[15:0]) iff (ins.trap == 0) {
+        // Compare the lowest 16 bits of current rd value to
+        // lowest 16 bits of previous rd value (which is the same as rs1 value for the current instruction)
+        bins rd_equal_val_hw_rs1  = {1}; // Cases where the lowest 16 bits of rd and rs1 are equal
+        bins rd_not_equal_val_hw_rs1  = {0}; // Cases where the lowest 16 bits of rd and rs1 are not equal
+    }
+
+    cmp_rd_rs1_val_lsb : coverpoint (ins.current.rd_val[7:0] == ins.prev.rd_val[7:0]) iff (ins.trap == 0) {
+        // Compare the least significant byte of current rd value to the
+        // least significant byte of previous rd value (which is the same as rs1 value for the current instruction)
+        bins rd_equal_val_lsb_rs1  = {1};  // Cases where the least significant byte of rd and rs1 are equal
+        bins rd_not_equal_val_lsb_rs1  = {0};  // Cases where the least significant byte of rd and rs1 are not equal
+    }
+
+    cmp_rd_rs1_val_w : coverpoint (ins.current.rd_val[31:0] == ins.prev.rd_val[31:0]) iff (ins.trap == 0) {
+        // Compare the lowest 32 bits of current rd value to the
+        // lowest 32 bits of previous rd value (which is the same as rs1 value for the current instruction)
+        bins rd_equal_val_w_rs1  = {1}; // Cases where the lowest 32 bits of rd and rs1 are equal
+        bins rd_not_equal_val_w_rs1  = {0}; // Cases where the lowest 32 bits of rd and rs1 are not equal
+    }
+
     cmp_rd_rs2 : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.current.rd == ins.current.rs2 & ins.trap == 0 )  {
         // Compare assignments of all registers
     }
@@ -257,12 +339,47 @@ covergroup Zacas_amocas_q_cg with function sample(ins_t ins);
         bins reg_pair[] = {[$:$]} with (item % 2 == 0);
     }
 
+    cmp_rd_rs1_pair_partial_val : coverpoint (
+            (ins.current.rd_val == ins.prev.rd_val) ^
+            (ins.current.rd_next_val == ins.prev.rd_next_val)
+        ) iff (ins.trap == 0)
+        {
+        // Cases where rd and rs1 have matching high or low halves but not both
+            bins rd_pair_partial_equal_val_rs1 = {1};
+            bins rd_pair_partial_not_equal_val_rs1 = {0};
+        }
+
     cmp_rd_rs1_rs2_nx0_pair : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.current.rd == ins.current.rs1 & ins.current.rd == ins.current.rs2 & ins.trap == 0 )  {
         // Compare assignments of all even registers excluding x0
         ignore_bins x0 = {x0};
         bins reg_pair[] = {[$:$]} with (item % 2 == 0);
     }
 
+cmp_rd_rs1_val_eq : coverpoint (ins.current.rd_val == ins.prev.rd_val) iff (ins.trap == 0) {
+    // Compare rd current to rd previous value (which is the same as rs1 value for the current instruction)
+}
+
+    cmp_rd_rs1_val_hw : coverpoint (ins.current.rd_val[15:0] == ins.prev.rd_val[15:0]) iff (ins.trap == 0) {
+        // Compare the lowest 16 bits of current rd value to
+        // lowest 16 bits of previous rd value (which is the same as rs1 value for the current instruction)
+        bins rd_equal_val_hw_rs1  = {1}; // Cases where the lowest 16 bits of rd and rs1 are equal
+        bins rd_not_equal_val_hw_rs1  = {0}; // Cases where the lowest 16 bits of rd and rs1 are not equal
+    }
+
+    cmp_rd_rs1_val_lsb : coverpoint (ins.current.rd_val[7:0] == ins.prev.rd_val[7:0]) iff (ins.trap == 0) {
+        // Compare the least significant byte of current rd value to the
+        // least significant byte of previous rd value (which is the same as rs1 value for the current instruction)
+        bins rd_equal_val_lsb_rs1  = {1};  // Cases where the least significant byte of rd and rs1 are equal
+        bins rd_not_equal_val_lsb_rs1  = {0};  // Cases where the least significant byte of rd and rs1 are not equal
+    }
+
+    cmp_rd_rs1_val_w : coverpoint (ins.current.rd_val[31:0] == ins.prev.rd_val[31:0]) iff (ins.trap == 0) {
+        // Compare the lowest 32 bits of current rd value to the
+        // lowest 32 bits of previous rd value (which is the same as rs1 value for the current instruction)
+        bins rd_equal_val_w_rs1  = {1}; // Cases where the lowest 32 bits of rd and rs1 are equal
+        bins rd_not_equal_val_w_rs1  = {0}; // Cases where the lowest 32 bits of rd and rs1 are not equal
+    }
+
     cmp_rd_rs2_pair : coverpoint ins.get_gpr_reg(ins.current.rd)  iff (ins.current.rd == ins.current.rs2 & ins.trap == 0 )  {
         // Compare assignments of all even registers
         bins reg_pair[] = {[$:$]} with (item % 2 == 0);