refactor(testgen): move dyn frm setup into formatters with random mode

Instead of patching tc.code in each coverpoint generator, move the
fcsr.frm setup and restore logic into the five FP instruction formatters
(FR, FR4, FI, F2X, X2F). When params.frm == "dyn", a random non-RNE
rounding mode (RTZ/RDN/RUP/RMM) is chosen via random.choice([1,2,3,4]),
appended to setup, and restored to RNE in check.

This centralises the fix so any future coverpoint using these formatters
automatically gets correct dyn handling without extra per-coverpoint code.
Remove the now-redundant dyn blocks from cp_frm.py and cr_fp_reg_edges.py.

Author: dev-aditya-hub

generators/testgen/src/testgen/coverpoints/cp_frm.py

@@ -27,12 +27,6 @@ def make_frm(instr_name: str, instr_type: str, coverpoint: str, test_data: TestD
         params = generate_random_params(test_data, instr_type, exclude_regs=[0], frm=frm_mode)
         desc = f"{coverpoint} (Test frm, mode = {frm_mode})"
         tc = format_single_testcase(instr_name, instr_type, test_data, params, desc, f"b{frm_mode}", coverpoint)
-        if frm_mode == "dyn":
-            # Set fcsr.frm to a non-default value (RDN=2) so that rm=111 (dyn) is forced
-            # to read a non-RNE frm from the CSR. Without this, fcsr.frm=0 at test time,
-            # making the dyn test identical to the rne test and allowing a DUT that
-            # hard-wires dyn=RNE to produce a false PASS.
-            tc.code = "fsrmi 0x2 # set fcsr.frm to RDN before dyn test\n" + tc.code + "\nfsrmi 0x0 # restore fcsr.frm to RNE"
         test_chunks.append(tc)
         return_test_regs(test_data, params)
 

generators/testgen/src/testgen/coverpoints/cr_fp_reg_edges.py

@@ -47,12 +47,6 @@ def make_cr_fs1_fs2_edges(instr_name: str, instr_type: str, coverpoint: str, tes
                 bin_name = f"fs1val={edge_val1:#x}, fs2val={edge_val2:#x}, frm={frm_mode}"
                 desc = f"{coverpoint} (Test source fs1 = {test_data.flen_format_str.format(edge_val1)} fs2 = {test_data.flen_format_str.format(edge_val2)}{f', frm = {frm_mode}' if frm_mode is not None else ''})"
                 tc = format_single_testcase(instr_name, instr_type, test_data, params, desc, bin_name, coverpoint)
-                if frm_mode == "dyn":
-                    # Set fcsr.frm to a non-default value (RDN=2) so that rm=111 (dyn) is
-                    # forced to read a non-RNE frm from the CSR. Without this, fcsr.frm=0
-                    # at test time, making the dyn test identical to the rne test and
-                    # allowing a DUT that hard-wires dyn=RNE to produce a false PASS.
-                    tc.code = "fsrmi 0x2 # set fcsr.frm to RDN before dyn test\n" + tc.code + "\nfsrmi 0x0 # restore fcsr.frm to RNE"
                 test_chunks.append(tc)
                 return_test_regs(test_data, params)
 
@@ -90,12 +84,6 @@ def make_cr_fs1_fs3_edges(instr_name: str, instr_type: str, coverpoint: str, tes
                 desc = f"{coverpoint} (Test source fs1 = {test_data.flen_format_str.format(edge_val1)} fs3 = {test_data.flen_format_str.format(edge_val2)}{f', frm = {frm_mode}' if frm_mode is not None else ''})"
                 bin_name = f"fs1val={edge_val1:#x}, fs3val={edge_val2:#x}, frm={frm_mode}"
                 tc = format_single_testcase(instr_name, instr_type, test_data, params, desc, bin_name, coverpoint)
-                if frm_mode == "dyn":
-                    # Set fcsr.frm to a non-default value (RDN=2) so that rm=111 (dyn) is
-                    # forced to read a non-RNE frm from the CSR. Without this, fcsr.frm=0
-                    # at test time, making the dyn test identical to the rne test and
-                    # allowing a DUT that hard-wires dyn=RNE to produce a false PASS.
-                    tc.code = "fsrmi 0x2 # set fcsr.frm to RDN before dyn test\n" + tc.code + "\nfsrmi 0x0 # restore fcsr.frm to RNE"
                 test_chunks.append(tc)
                 return_test_regs(test_data, params)
 

generators/testgen/src/testgen/formatters/types/f2x_type.py

@@ -5,6 +5,8 @@
 # SPDX-License-Identifier: Apache-2.0
 ##################################
 
+import random
+
 from testgen.asm.helpers import load_float_reg, write_sigupd
 from testgen.data.params import InstructionParams
 from testgen.data.state import TestData
@@ -38,4 +40,8 @@ def format_f2x_type(
         write_sigupd(params.rd, test_data, "int"),
         write_sigupd(None, test_data, "fflags"),
     ]
+    if params.frm == "dyn":
+        rand_frm = random.choice([1, 2, 3, 4])
+        setup.append(f"fsrmi {rand_frm}")
+        check.append("fsrmi 0x0")
     return (setup, test, check)

generators/testgen/src/testgen/formatters/types/fi_type.py

@@ -5,6 +5,8 @@
 # SPDX-License-Identifier: Apache-2.0
 ##################################
 
+import random
+
 from testgen.asm.helpers import load_float_reg, write_sigupd
 from testgen.data.params import InstructionParams
 from testgen.data.state import TestData
@@ -29,4 +31,8 @@ def format_fi_type(
         f"{instr_name} f{params.fd}, f{params.fs1}{frm} # perform operation",
     ]
     check = [write_sigupd(params.fd, test_data, "float")]
+    if params.frm == "dyn":
+        rand_frm = random.choice([1, 2, 3, 4])
+        setup.append(f"fsrmi {rand_frm}")
+        check.append("fsrmi 0x0")
     return (setup, test, check)

generators/testgen/src/testgen/formatters/types/fr4_type.py

@@ -5,6 +5,8 @@
 # SPDX-License-Identifier: Apache-2.0
 ##################################
 
+import random
+
 from testgen.asm.helpers import load_float_reg, write_sigupd
 from testgen.data.params import InstructionParams
 from testgen.data.state import TestData
@@ -33,4 +35,8 @@ def format_fr4_type(
         f"{instr_name} f{params.fd}, f{params.fs1}, f{params.fs2}, f{params.fs3}{frm} # perform operation",
     ]
     check = [write_sigupd(params.fd, test_data, "float")]
+    if params.frm == "dyn":
+        rand_frm = random.choice([1, 2, 3, 4])
+        setup.append(f"fsrmi {rand_frm}")
+        check.append("fsrmi 0x0")
     return (setup, test, check)

generators/testgen/src/testgen/formatters/types/fr_type.py

@@ -5,6 +5,8 @@
 # SPDX-License-Identifier: Apache-2.0
 ##################################
 
+import random
+
 from testgen.asm.helpers import load_float_reg, write_sigupd
 from testgen.data.params import InstructionParams
 from testgen.data.state import TestData
@@ -31,4 +33,8 @@ def format_fr_type(
         f"{instr_name} f{params.fd}, f{params.fs1}, f{params.fs2}{frm} # perform operation",
     ]
     check = [write_sigupd(params.fd, test_data, "float")]
+    if params.frm == "dyn":
+        rand_frm = random.choice([1, 2, 3, 4])
+        setup.append(f"fsrmi {rand_frm}")
+        check.append("fsrmi 0x0")
     return (setup, test, check)

generators/testgen/src/testgen/formatters/types/x2f_type.py

@@ -5,6 +5,8 @@
 # SPDX-License-Identifier: Apache-2.0
 ##################################
 
+import random
+
 from testgen.asm.helpers import load_int_reg, write_sigupd
 from testgen.data.params import InstructionParams
 from testgen.data.state import TestData
@@ -29,4 +31,8 @@ def format_x2f_type(
         f"{instr_name} f{params.fd}, x{params.rs1}{frm} # perform operation",
     ]
     check = [write_sigupd(params.fd, test_data, "float")]
+    if params.frm == "dyn":
+        rand_frm = random.choice([1, 2, 3, 4])
+        setup.append(f"fsrmi {rand_frm}")
+        check.append("fsrmi 0x0")
     return (setup, test, check)