Specs: docs/SPECS.md. Design gates:
docs/DESIGN_ASSURANCE.md.
Lessons from the v1.0 order (July 2026) are in docs/HISTORY.md.
For V3, fab from the pinned manufacturing board under ci/artifacts/
(after verify + pcbkit:assure), not from unrouted export:kicad output.
- Confirm revision: V3 from tscircuit (not historical Rev 1.0
fab/). -
git statusis clean for the commit you will tag. -
bun install && bun run verifygreen. -
bun run pcbkit:assuregreen againstci/artifacts/v3-manufacturing.kicad_pcb. Open that.kicad_proin KiCad; DRC manufacturing categories clean (USB footprint-internal waivers only). Vias ≥ 0.6 / 0.3 mm. - Manual rows in
docs/DESIGN_ASSURANCE.mdsigned off (F6P6, INA, RGB). - Visual check in KiCad — connectors, 240×47 mm outline, status LEDs aligned with ports.
- Check JLCPCB assembly stock (not just LCSC) for every Extended part:
CH32V203F6P6 (
C3040880), INA3221 (C181255), RGB LED (C5119723), HT7533-1 (C2686823). - Prefer Basic passives. Record substitutions in the BOM immediately (do not invent a second specs doc).
- Upload V3 gerbers/BOM/CPL from
generated/(or refreshedfab/). - Board: 2 layers, 1.6 mm FR-4, 240×47 mm, assembly top.
- Every BOM line confirmed; resolve inventory shortages per section 2.
- Polarized parts and IC pin-1 correct.
- Vertical USB-C plugs centered; MCU TSSOP-20 orientation correct.
- USB1 PD receptacle opening faces the left edge (pads inboard), same as barrel jack — not flipped inboard.
- BOOT switch SW1 accessible; nothing off-board.
- Screenshot final BOM match page.
- Tag the commit (
git tag v3.0 && git push --tags) and attach fab zips to a GitHub release.
- Power via USB1 or limited bench supply; check
rail_3v3and both 5 V rails. - Flash firmware over USB1 + BOOT0 with
wchisp(barrel unplugged). Seefirmware/status-controller/README.md. - Confirm OE keeps LEDs dark until firmware enables outputs; calibrate
thresholds in
status_config.hagainst a real bar (meanings indocs/SPECS.md).