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config ESP_HOSTED_ENABLED
bool "Enable ESP-Hosted component"
default y if ESP_WIFI_REMOTE_ENABLED && ESP_WIFI_REMOTE_LIBRARY_HOSTED
default n
help
Enable the esp-hosted component, allowing this device to act as a
Wi-Fi co-processor for a host MCU. Disable to exclude esp-hosted
from the build entirely.
menu "ESP-Hosted config"
depends on ESP_HOSTED_ENABLED
choice ESP_HOSTED_CP_TARGET
bool "Choose the Co-processor to use"
config ESP_HOSTED_CP_TARGET_ESP32
depends on SLAVE_IDF_TARGET_ESP32
bool "ESP32 (fetched from Wi-Fi Remote Component)"
config ESP_HOSTED_CP_TARGET_ESP32S2
depends on SLAVE_IDF_TARGET_ESP32S2
bool "ESP32S2 (fetched from Wi-Fi Remote Component)"
config ESP_HOSTED_CP_TARGET_ESP32S3
depends on SLAVE_IDF_TARGET_ESP32S3
bool "ESP32S3 (fetched from Wi-Fi Remote Component)"
config ESP_HOSTED_CP_TARGET_ESP32C2
depends on SLAVE_IDF_TARGET_ESP32C2
bool "ESP32-C2 (fetched from Wi-Fi Remote Component)"
config ESP_HOSTED_CP_TARGET_ESP32C3
depends on SLAVE_IDF_TARGET_ESP32C3
bool "ESP32-C3 (fetched from Wi-Fi Remote Component)"
config ESP_HOSTED_CP_TARGET_ESP32C6
depends on SLAVE_IDF_TARGET_ESP32C6
bool "ESP32-C6 (fetched from Wi-Fi Remote Component)"
config ESP_HOSTED_CP_TARGET_ESP32C5
depends on SLAVE_IDF_TARGET_ESP32C5
bool "ESP32-C5 (fetched from Wi-Fi Remote Component)"
config ESP_HOSTED_CP_TARGET_ESP32C61
depends on SLAVE_IDF_TARGET_ESP32C61
bool "ESP32-C61 (fetched from Wi-Fi Remote Component)"
config ESP_HOSTED_CP_TARGET_ESP32H2
bool "ESP32-H2"
# Note: not yet supported on ESP32-H4
# - Bluetooth
# - SPI interface
config ESP_HOSTED_CP_TARGET_ESP32H4
bool "ESP32-H4"
endchoice
### To be removed in the future after further testing
comment "ESP32-H4 currently does not support Bluetooth and SPI as Hosted transport"
depends on ESP_HOSTED_CP_TARGET_ESP32H4
### config to show / hide Wi-Fi options in Kconfig
### Wi-Fi is not supported if target is ESP32-H2, H4
config ESP_HOSTED_PRIV_ENABLE_WIFI_OPTIONS
bool
default n if ESP_HOSTED_CP_TARGET_ESP32H2 || ESP_HOSTED_CP_TARGET_ESP32H4
default y
# Show the Co-processor selected
comment "ESP32 is Co-processor Target from Wi-Fi Remote Component"
depends on ESP_HOSTED_CP_TARGET_ESP32
comment "ESP32-S2 is Co-processor Target from Wi-Fi Remote Component"
depends on ESP_HOSTED_CP_TARGET_ESP32S2
comment "ESP32-S3 is Co-processor Target from Wi-Fi Remote Component"
depends on ESP_HOSTED_CP_TARGET_ESP32S3
comment "ESP32-C2 is Co-processor Target from Wi-Fi Remote Component"
depends on ESP_HOSTED_CP_TARGET_ESP32C2
comment "ESP32-C3 is Co-processor Target from Wi-Fi Remote Component"
depends on ESP_HOSTED_CP_TARGET_ESP32C3
comment "ESP32-C6 is Co-processor Target from Wi-Fi Remote Component"
depends on ESP_HOSTED_CP_TARGET_ESP32C6
comment "ESP32-C5 is Co-processor Target from Wi-Fi Remote Component"
depends on ESP_HOSTED_CP_TARGET_ESP32C5
comment "ESP32-C61 is Co-processor Target from Wi-Fi Remote Component"
depends on ESP_HOSTED_CP_TARGET_ESP32C61
comment "ESP32-H2 is Co-processor Target"
depends on ESP_HOSTED_CP_TARGET_ESP32H2
comment "ESP32-H4 is Co-processor Target"
depends on ESP_HOSTED_CP_TARGET_ESP32H4
config ESP_HOSTED_IDF_SLAVE_TARGET
string
default "esp32" if ESP_HOSTED_CP_TARGET_ESP32
default "esp32s2" if ESP_HOSTED_CP_TARGET_ESP32S2
default "esp32s3" if ESP_HOSTED_CP_TARGET_ESP32S3
default "esp32c2" if ESP_HOSTED_CP_TARGET_ESP32C2
default "esp32c3" if ESP_HOSTED_CP_TARGET_ESP32C3
default "esp32c6" if ESP_HOSTED_CP_TARGET_ESP32C6
default "esp32c5" if ESP_HOSTED_CP_TARGET_ESP32C5
default "esp32c61" if ESP_HOSTED_CP_TARGET_ESP32C61
default "esp32h2" if ESP_HOSTED_CP_TARGET_ESP32H2
default "esp32h4" if ESP_HOSTED_CP_TARGET_ESP32H4
default "invalid"
choice ESP_HOSTED_P4_DEV_BOARD
bool "Configure GPIOs for Development Board"
depends on IDF_TARGET_ESP32P4
default ESP_HOSTED_P4_DEV_BOARD_NONE
help
Sets GPIOs used for transport on these ESP32-P4 Development Boards
- ESP32-P4/P4X Function_EV_Board with on-board ESP32-C6
- ESP32-P4 Function_EV_Board with ESP32-C5 on a EV board
- ESP32-P4 Function_EV_Board with ESP32-C2 on a EV board
- ESP32-P4-C5 Code Board with on-board ESP32-C5
- ESP32-P4X Function_EV_Board with on-board ESP32-C5
Select "No development board" if you want to modify GPIOs used
config ESP_HOSTED_P4_DEV_BOARD_NONE
bool "No development board"
config ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD
depends on ESP_HOSTED_CP_TARGET_ESP32C6 || ESP_HOSTED_CP_TARGET_ESP32C5 || ESP_HOSTED_CP_TARGET_ESP32C2
bool "ESP32-P4/P4X-Function-EV-Board with on-board C6 or C5/C2 on EV board"
config ESP32P4_EYE_C6_BOARD
depends on SLAVE_IDF_TARGET_ESP32C6
bool "ESP32-P4-EYE Board with on-board C6"
config ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
depends on ESP_HOSTED_CP_TARGET_ESP32C5
bool "ESP32-P4X-Function-EV-Board with on-board C5"
config ESP32P4_TAB5_C6_BOARD
depends on SLAVE_IDF_TARGET_ESP32C6
bool "M5Stack Tab5 with on-board ESP32-C6"
config ESP_HOSTED_P4_C5_CORE_BOARD
depends on ESP_HOSTED_CP_TARGET_ESP32C5
bool "ESP32-P4-C5 Core Board with on-board C5"
config ESP_HOSTED_P4_C6_CORE_BOARD
depends on ESP_HOSTED_CP_TARGET_ESP32C6
bool "ESP32-P4-C6 Core Board with on-board C6"
config ESP_HOSTED_P4_C61_CORE_BOARD
depends on ESP_HOSTED_CP_TARGET_ESP32C61
bool "ESP32-P4-C61 Core Board with on-board C61"
endchoice
# y if SDIO Transport is available, based on host and slave selection
config ESP_HOSTED_PRIV_SDIO_OPTION
bool
default y if (IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32P4) && (ESP_HOSTED_CP_TARGET_ESP32 || ESP_HOSTED_CP_TARGET_ESP32C6 || ESP_HOSTED_CP_TARGET_ESP32C5 || ESP_HOSTED_CP_TARGET_ESP32C61)
default n
# y if SPI HD Transport is available, based on host and slave selection
config ESP_HOSTED_PRIV_SPI_HD_OPTION
bool
default n if (IDF_TARGET_ESP32 || ESP_HOSTED_CP_TARGET_ESP32 || ESP_HOSTED_CP_TARGET_ESP32H4)
default y
choice ESP_HOSTED_HOST_INTERFACE
bool "Transport layer"
default ESP_HOSTED_SDIO_HOST_INTERFACE if ESP_HOSTED_PRIV_SDIO_OPTION
default ESP_HOSTED_SPI_HOST_INTERFACE
help
Bus interface to be used for communication with the host
config ESP_HOSTED_SPI_HOST_INTERFACE
depends on !ESP_HOSTED_CP_TARGET_ESP32H4 # SPI currently not working
bool "SPI Full-duplex"
help
Enable/Disable SPI Full-duplex host interface
config ESP_HOSTED_SDIO_HOST_INTERFACE
depends on ESP_HOSTED_PRIV_SDIO_OPTION
bool "SDIO"
help
Enable/Disable SDIO host interface
# SPI Half Duplex is not supported in ESP32
config ESP_HOSTED_SPI_HD_HOST_INTERFACE
depends on ESP_HOSTED_PRIV_SPI_HD_OPTION
bool "SPI Half-duplex"
help
Enable/Disable SPI Half-duplex host interface
config ESP_HOSTED_UART_HOST_INTERFACE
bool "UART"
help
Enable/Disable UART host interface
endchoice
menu "SPI Configuration"
depends on ESP_HOSTED_SPI_HOST_INTERFACE
choice ESP_HOSTED_SPI_PRIV_MODE_ESP32
depends on ESP_HOSTED_CP_TARGET_ESP32
bool "Host SPI mode"
default ESP_HOSTED_SPI_PRIV_MODE_2_ESP32
config ESP_HOSTED_SPI_PRIV_MODE_0_ESP32
bool "Host SPI mode 0"
config ESP_HOSTED_SPI_PRIV_MODE_1_ESP32
bool "Host SPI mode 1"
config ESP_HOSTED_SPI_PRIV_MODE_2_ESP32
bool "Host SPI mode 2"
config ESP_HOSTED_SPI_PRIV_MODE_3_ESP32
bool "Host SPI mode 3"
endchoice
choice ESP_HOSTED_SPI_PRIV_MODE_ESP32XX
depends on !ESP_HOSTED_CP_TARGET_ESP32
bool "Host SPI mode"
default ESP_HOSTED_SPI_PRIV_MODE_3_ESP32XX
config ESP_HOSTED_SPI_PRIV_MODE_0_ESP32XX
bool "Host SPI mode 0"
config ESP_HOSTED_SPI_PRIV_MODE_1_ESP32XX
bool "Host SPI mode 1"
config ESP_HOSTED_SPI_PRIV_MODE_2_ESP32XX
bool "Host SPI mode 2"
config ESP_HOSTED_SPI_PRIV_MODE_3_ESP32XX
bool "Host SPI mode 3"
endchoice
config ESP_HOSTED_SPI_MODE
int
default 0 if ESP_HOSTED_SPI_PRIV_MODE_0_ESP32
default 1 if ESP_HOSTED_SPI_PRIV_MODE_1_ESP32
default 2 if ESP_HOSTED_SPI_PRIV_MODE_2_ESP32
default 3 if ESP_HOSTED_SPI_PRIV_MODE_3_ESP32
default 0 if ESP_HOSTED_SPI_PRIV_MODE_0_ESP32XX
default 1 if ESP_HOSTED_SPI_PRIV_MODE_1_ESP32XX
default 2 if ESP_HOSTED_SPI_PRIV_MODE_2_ESP32XX
default 3 if ESP_HOSTED_SPI_PRIV_MODE_3_ESP32XX
choice ESP_HOSTED_SPI_CONTROLLER
bool "Host SPI controller to use"
default ESP_HOSTED_SPI_HSPI
config ESP_HOSTED_SPI_HSPI
bool "HSPI/FSPI"
help
"HSPI/FSPI: SPI_controller_1"
config ESP_HOSTED_SPI_VSPI
depends on IDF_TARGET_ESP32
bool "VSPI"
help
"VSPI: SPI_controller_2"
endchoice
config ESP_HOSTED_SPI_CONTROLLER
int
default 2 if ESP_HOSTED_SPI_VSPI
default 1
menu "Host SPI GPIOs Config"
choice ESP_HOSTED_SPI_HANDSHAKE_GPIO_CONFIG
bool "Handshake GPIO Config"
default ESP_HOSTED_HS_ACTIVE_HIGH
config ESP_HOSTED_HS_ACTIVE_HIGH
bool "HS: Active High"
config ESP_HOSTED_HS_ACTIVE_LOW
bool "HS: Active Low"
endchoice
choice ESP_HOSTED_SPI_DATAREADY__GPIO_CONFIG
bool "DataReady GPIO Config"
default ESP_HOSTED_DR_ACTIVE_HIGH
config ESP_HOSTED_DR_ACTIVE_HIGH
bool "DR: Active High"
config ESP_HOSTED_DR_ACTIVE_LOW
bool "DR: Active Low"
endchoice
choice ESP_HOSTED_SPI_RESET_GPIO_CONFIG
bool "Reset GPIO Config"
default ESP_HOSTED_SPI_RESET_ACTIVE_HIGH
help
"If Active High, High->Low->High will trigger reset (Low will trigger reset)
If Active Low, Low->High->Low will trigger reset (High will trigger reset)"
config ESP_HOSTED_SPI_RESET_ACTIVE_HIGH
bool "RESET: Active High"
config ESP_HOSTED_SPI_RESET_ACTIVE_LOW
bool "RESET: Active Low"
endchoice
config ESP_HOSTED_SPI_MOSI_RANGE_MIN
int
default 49 if ESP_HOSTED_P4_C5_CORE_BOARD
default 50 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 29 if ESP32P4_EYE_C6_BOARD
default 14 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 23 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 23 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 14 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 0
config ESP_HOSTED_SPI_MOSI_RANGE_MAX
int
default 49 if ESP_HOSTED_P4_C5_CORE_BOARD
default 50 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 29 if ESP32P4_EYE_C6_BOARD
default 14 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 23 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 23 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 14 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 100
config ESP_HOSTED_SPI_HSPI_GPIO_MOSI
depends on ESP_HOSTED_SPI_HSPI
int "GPIO pin for Host MOSI"
default 49 if ESP_HOSTED_P4_C5_CORE_BOARD
default 50 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 29 if ESP32P4_EYE_C6_BOARD
default 8 if IDF_TARGET_ESP32P4
default 13 if IDF_TARGET_ESP32
default 11 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
default 5 if IDF_TARGET_ESP32H2
default 7
range ESP_HOSTED_SPI_MOSI_RANGE_MIN ESP_HOSTED_SPI_MOSI_RANGE_MAX
help
SPI controller Host MOSI
config ESP_HOSTED_SPI_MISO_RANGE_MIN
int
default 48 if ESP_HOSTED_P4_C5_CORE_BOARD
default 49 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 30 if ESP32P4_EYE_C6_BOARD
default 15 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 22 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 22 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 15 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 0
config ESP_HOSTED_SPI_MISO_RANGE_MAX
int
default 48 if ESP_HOSTED_P4_C5_CORE_BOARD
default 49 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 30 if ESP32P4_EYE_C6_BOARD
default 15 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 22 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 22 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 15 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 100
config ESP_HOSTED_SPI_HSPI_GPIO_MISO
depends on ESP_HOSTED_SPI_HSPI
int "GPIO pin for Host MISO"
default 48 if ESP_HOSTED_P4_C5_CORE_BOARD
default 49 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 30 if ESP32P4_EYE_C6_BOARD
default 10 if IDF_TARGET_ESP32P4
default 12 if IDF_TARGET_ESP32
default 13 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
default 0 if IDF_TARGET_ESP32H2
default 2
range ESP_HOSTED_SPI_MISO_RANGE_MIN ESP_HOSTED_SPI_MISO_RANGE_MAX
help
SPI controller Host MISO
config ESP_HOSTED_SPI_CLK_RANGE_MIN
int
default 50 if ESP_HOSTED_P4_C5_CORE_BOARD
default 51 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 28 if ESP32P4_EYE_C6_BOARD
default 18 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 33 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 33 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 18 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 0
config ESP_HOSTED_SPI_CLK_RANGE_MAX
int
default 50 if ESP_HOSTED_P4_C5_CORE_BOARD
default 51 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 28 if ESP32P4_EYE_C6_BOARD
default 18 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 33 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 33 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 18 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 100
config ESP_HOSTED_SPI_HSPI_GPIO_CLK
depends on ESP_HOSTED_SPI_HSPI
int "GPIO pin for Host CLK"
default 50 if ESP_HOSTED_P4_C5_CORE_BOARD
default 51 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 28 if ESP32P4_EYE_C6_BOARD
default 9 if IDF_TARGET_ESP32P4
default 14 if IDF_TARGET_ESP32
default 12 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
default 4 if IDF_TARGET_ESP32H2
default 6
range ESP_HOSTED_SPI_CLK_RANGE_MIN ESP_HOSTED_SPI_CLK_RANGE_MAX
help
SPI controller Host CLK
config ESP_HOSTED_SPI_CS_RANGE_MIN
int
default 51 if ESP_HOSTED_P4_C5_CORE_BOARD
default 52 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 27 if ESP32P4_EYE_C6_BOARD
default 19 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 4 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 4 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 19 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 0
config ESP_HOSTED_SPI_CS_RANGE_MAX
int
default 51 if ESP_HOSTED_P4_C5_CORE_BOARD
default 52 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 27 if ESP32P4_EYE_C6_BOARD
default 19 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 4 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 4 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 19 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 100
config ESP_HOSTED_SPI_HSPI_GPIO_CS
depends on ESP_HOSTED_SPI_HSPI
int "GPIO pin for Host CS"
default 51 if ESP_HOSTED_P4_C5_CORE_BOARD
default 52 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 27 if ESP32P4_EYE_C6_BOARD
default 7 if IDF_TARGET_ESP32P4
default 15 if IDF_TARGET_ESP32
default 10 if IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
default 1 if IDF_TARGET_ESP32H2
default 10
range ESP_HOSTED_SPI_CS_RANGE_MIN ESP_HOSTED_SPI_CS_RANGE_MAX
help
SPI controller Host CS
config ESP_HOSTED_SPI_VSPI_GPIO_MOSI
depends on ESP_HOSTED_SPI_VSPI
int "GPIO pin for Host MOSI"
default 23
help
SPI controller Host MOSI
config ESP_HOSTED_SPI_VSPI_GPIO_MISO
depends on ESP_HOSTED_SPI_VSPI
int "GPIO pin for Host MISO"
default 19
help
SPI controller Host MISO
config ESP_HOSTED_SPI_VSPI_GPIO_CLK
depends on ESP_HOSTED_SPI_VSPI
int "GPIO pin for Host CLK"
default 18
help
SPI controller Host CLK
config ESP_HOSTED_SPI_VSPI_GPIO_CS
depends on ESP_HOSTED_SPI_VSPI
int "GPIO pin for Host CS"
default 5
help
SPI controller Host CS
config ESP_HOSTED_SPI_GPIO_MOSI
int
default ESP_HOSTED_SPI_VSPI_GPIO_MOSI if ESP_HOSTED_SPI_VSPI
default ESP_HOSTED_SPI_HSPI_GPIO_MOSI
config ESP_HOSTED_SPI_GPIO_MISO
int
default ESP_HOSTED_SPI_VSPI_GPIO_MISO if ESP_HOSTED_SPI_VSPI
default ESP_HOSTED_SPI_HSPI_GPIO_MISO
config ESP_HOSTED_SPI_GPIO_CLK
int
default ESP_HOSTED_SPI_VSPI_GPIO_CLK if ESP_HOSTED_SPI_VSPI
default ESP_HOSTED_SPI_HSPI_GPIO_CLK
config ESP_HOSTED_SPI_GPIO_CS
int
default ESP_HOSTED_SPI_VSPI_GPIO_CS if ESP_HOSTED_SPI_VSPI
default ESP_HOSTED_SPI_HSPI_GPIO_CS
config ESP_HOSTED_SPI_HANDSHAKE_RANGE_MIN
int
default 53 if ESP_HOSTED_P4_C5_CORE_BOARD
default 48 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 31 if ESP32P4_EYE_C6_BOARD
default 16 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 21 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 21 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 16 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 0
config ESP_HOSTED_SPI_HANDSHAKE_RANGE_MAX
int
default 53 if ESP_HOSTED_P4_C5_CORE_BOARD
default 48 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 31 if ESP32P4_EYE_C6_BOARD
default 16 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 21 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 21 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 16 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 100
config ESP_HOSTED_SPI_GPIO_HANDSHAKE
int "GPIO pin for handshake"
default 53 if ESP_HOSTED_P4_C5_CORE_BOARD
default 48 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 31 if ESP32P4_EYE_C6_BOARD
default 6 if IDF_TARGET_ESP32P4
default 3 if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32C6
default 17 if IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32S2
default 22 if IDF_TARGET_ESP32H2
default 26
range ESP_HOSTED_SPI_HANDSHAKE_RANGE_MIN ESP_HOSTED_SPI_HANDSHAKE_RANGE_MAX
help
GPIO pin to use for handshake with other spi controller
config ESP_HOSTED_SPI_DATA_READY_RANGE_MIN
int
default 52 if ESP_HOSTED_P4_C5_CORE_BOARD
default 47 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 32 if ESP32P4_EYE_C6_BOARD
default 17 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 32 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 32 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 17 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 0
config ESP_HOSTED_SPI_DATA_READY_RANGE_MAX
int
default 52 if ESP_HOSTED_P4_C5_CORE_BOARD
default 47 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 32 if ESP32P4_EYE_C6_BOARD
default 17 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 32 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 32 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 17 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 100
config ESP_HOSTED_SPI_GPIO_DATA_READY
int "GPIO pin for data ready interrupt"
default 52 if ESP_HOSTED_P4_C5_CORE_BOARD
default 47 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 32 if ESP32P4_EYE_C6_BOARD
default 11 if IDF_TARGET_ESP32P4
default 12 if IDF_TARGET_ESP32H2
default 4
range ESP_HOSTED_SPI_DATA_READY_RANGE_MIN ESP_HOSTED_SPI_DATA_READY_RANGE_MAX
help
GPIO pin for indicating host that SPI slave has data to be read by host
config ESP_HOSTED_SPI_RESET_RANGE_MIN
int
default 54 if ESP_HOSTED_P4_C5_CORE_BOARD || ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 9 if ESP32P4_EYE_C6_BOARD
default 54 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 53 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 53 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 54 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 0
config ESP_HOSTED_SPI_RESET_RANGE_MAX
int
default 54 if ESP_HOSTED_P4_C5_CORE_BOARD || ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 9 if ESP32P4_EYE_C6_BOARD
default 54 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 53 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 53 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C2
default 54 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 100
config ESP_HOSTED_SPI_GPIO_RESET_SLAVE
int "GPIO pin for Resetting slave ESP"
default 54 if ESP_HOSTED_P4_C5_CORE_BOARD || ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 9 if ESP32P4_EYE_C6_BOARD
default 12 if IDF_TARGET_ESP32P4
default 10 if IDF_TARGET_ESP32H2
default 5
range ESP_HOSTED_SPI_RESET_RANGE_MIN ESP_HOSTED_SPI_RESET_RANGE_MAX
help
GPIO pin for Resetting ESP SPI slave device. Should be connected to RST/EN of ESP SPI slave device.
endmenu
ESP32XX_SPI_CLK_FREQ_RANGE_MIN := 1
ESP32_SPI_CLK_FREQ_RANGE_MAX := 10
ESP32H2_SPI_CLK_FREQ_RANGE_MAX := 32
ESP32C6_SPI_CLK_FREQ_RANGE_MAX := 40
ESP32XX_SPI_CLK_FREQ_RANGE_MAX := 40
config ESP_HOSTED_SPI_FREQ_ESP32
depends on ESP_HOSTED_CP_TARGET_ESP32
int "SPI Clock Freq (MHz)"
default 10
range $(ESP32XX_SPI_CLK_FREQ_RANGE_MIN) $(ESP32_SPI_CLK_FREQ_RANGE_MAX)
help
"Optimize SPI CLK by increasing till host practically can support"
config ESP_HOSTED_SPI_FREQ_ESP32H2
depends on ESP_HOSTED_CP_TARGET_ESP32H2
int "SPI Clock Freq (MHz)"
default 32 if IDF_TARGET_ESP32P4 #config for ESP32-P4 Function_EV_Board
default 26
range $(ESP32XX_SPI_CLK_FREQ_RANGE_MIN) $(ESP32H2_SPI_CLK_FREQ_RANGE_MAX)
help
"Optimize SPI CLK by increasing till host practically can support"
config ESP_HOSTED_SPI_FREQ_ESP32C6
depends on ESP_HOSTED_CP_TARGET_ESP32C6
int "SPI Clock Freq (MHz)"
default 40 if IDF_TARGET_ESP32P4 #config for ESP32-P4 Function_EV_Board
default 26
range $(ESP32XX_SPI_CLK_FREQ_RANGE_MIN) $(ESP32C6_SPI_CLK_FREQ_RANGE_MAX)
help
"Optimize SPI CLK by increasing till host practically can support"
config ESP_HOSTED_SPI_FREQ_ESP32XX
depends on ESP_HOSTED_CP_TARGET_ESP32C2 || ESP_HOSTED_CP_TARGET_ESP32C3 || ESP_HOSTED_CP_TARGET_ESP32S2 || ESP_HOSTED_CP_TARGET_ESP32S3 || ESP_HOSTED_CP_TARGET_ESP32C5 || ESP_HOSTED_CP_TARGET_ESP32C61
int "SPI Clock Freq"
default 40 if ESP_HOSTED_CP_TARGET_ESP32C2 || ESP_HOSTED_CP_TARGET_ESP32C3 || ESP_HOSTED_CP_TARGET_ESP32S2 || ESP_HOSTED_CP_TARGET_ESP32S3 || ESP_HOSTED_CP_TARGET_ESP32C5 || ESP_HOSTED_CP_TARGET_ESP32C61
range $(ESP32XX_SPI_CLK_FREQ_RANGE_MIN) $(ESP32XX_SPI_CLK_FREQ_RANGE_MAX)
help
"Optimize SPI CLK by increasing till host practically can support"
config ESP_HOSTED_SPI_CLK_FREQ
int
default ESP_HOSTED_SPI_FREQ_ESP32 if ESP_HOSTED_CP_TARGET_ESP32
default ESP_HOSTED_SPI_FREQ_ESP32C6 if ESP_HOSTED_CP_TARGET_ESP32C6
default ESP_HOSTED_SPI_FREQ_ESP32H2 if ESP_HOSTED_CP_TARGET_ESP32H2
default ESP_HOSTED_SPI_FREQ_ESP32XX if ESP_HOSTED_CP_TARGET_ESP32C2 || ESP_HOSTED_CP_TARGET_ESP32C3 || ESP_HOSTED_CP_TARGET_ESP32S2 || ESP_HOSTED_CP_TARGET_ESP32S3 || ESP_HOSTED_CP_TARGET_ESP32C5 || ESP_HOSTED_CP_TARGET_ESP32C61
help
"Optimize SPI CLK by increasing till host practically can support"
config ESP_HOSTED_SPI_TX_Q_SIZE
int "ESP to Host SPI queue size"
default 7 if ESP_HOSTED_HOST_OT_ENABLE
default 15
help
Very small tx queue will lower ESP -- SPI --> Host data rate
config ESP_HOSTED_SPI_RX_Q_SIZE
int "Host to ESP SPI queue size"
default 7 if ESP_HOSTED_HOST_OT_ENABLE
default 15
help
Very small RX queue will lower ESP <-- SPI -- Host data rate
endmenu
menu "Hosted SDIO Configuration"
depends on ESP_HOSTED_SDIO_HOST_INTERFACE
choice ESP_HOSTED_SDIO_RESET_GPIO_CONFIG
bool "RESET GPIO Config"
# M5Stack Tab5's C6 reset circuit is active-low; with the
# active-high default the slave never leaves reset and SDIO
# enumeration times out (sdmmc send_op_cond 0x107).
default ESP_HOSTED_SDIO_RESET_ACTIVE_LOW if ESP32P4_TAB5_C6_BOARD
default ESP_HOSTED_SDIO_RESET_ACTIVE_HIGH
help
"If Active High, High->Low->High will trigger reset (Low will trigger reset)
If Active Low, Low->High->Low will trigger reset (High will trigger reset)"
config ESP_HOSTED_SDIO_RESET_ACTIVE_HIGH
bool "RESET: Active High"
config ESP_HOSTED_SDIO_RESET_ACTIVE_LOW
bool "RESET: Active Low"
endchoice
choice ESP_HOSTED_SDIO_RX_OPTIMIZATION
bool "SDIO Receive Optimization"
default ESP_HOSTED_SDIO_OPTIMIZATION_RX_STREAMING_MODE
config ESP_HOSTED_SDIO_OPTIMIZATION_RX_NONE
bool "No optimization"
help
Use SDIO as is, with no optimizations.
config ESP_HOSTED_SDIO_OPTIMIZATION_RX_MAX_SIZE
bool "Always Rx Max Packet size"
help
Always read max Rx Packet Size (512 * 3 bytes). This saves one SDIO
transaction (get Rx Packet Size) when reading data from slave by
always transferring a fixed amount of data. Extra data at end of valid
packet data is discarded.
config ESP_HOSTED_SDIO_OPTIMIZATION_RX_STREAMING_MODE
bool "Use Streaming Mode"
help
Receive a stream of queued data from the slave, made up of one or more
packets of data. Host extracts packets from the stream. This improves
SDIO read performance by doing one large read transaction instead of
many smaller read transactions for each packet.
(Note: requires slave to support streaming mode.)
endchoice
choice
prompt "SDIO Slot To Use"
default ESP_HOSTED_SDIO_SLOT_1
help
On the ESP32-P4 EV Board:
- Slot 0 connects to the MicroSD Card slot
- Slot 1 connects to the on-board ESP32-C6
For the ESP32, Slot 0 is usually occupied by SPI Flash and not usable for SDIO.
For the ESP32-P4, Slot 0 is IOMUXed and GPIO values cannot be changed
config ESP_HOSTED_SDIO_SLOT_0
depends on IDF_TARGET_ESP32P4 || IDF_TARGET_ESP32S3
bool "Slot 0"
config ESP_HOSTED_SDIO_SLOT_1
bool "Slot 1"
endchoice
config ESP_HOSTED_SDIO_SLOT
int
default 0 if ESP_HOSTED_SDIO_SLOT_0
default 1 if ESP_HOSTED_SDIO_SLOT_1
config ESP_HOSTED_SD_PWR_CTRL_LDO_INTERNAL_IO
depends on SOC_SDMMC_IO_POWER_EXTERNAL
bool "SDIO power supply comes from internal LDO IO (READ HELP!)"
default n
help
Only needed when the SDIO module is connected to specific IO pins which can be used for high-speed SDIO.
Please read the schematic first and check if the SD VDD is connected to any internal LDO output.
Unselect this option if the SDIO is powered by an external power supply.
For ESP32-P4 EV Board, SDMMC slot 0 may require internal LDO output.
config ESP_HOSTED_SD_PWR_CTRL_LDO_IO_ID
depends on SOC_SDMMC_IO_POWER_EXTERNAL && ESP_HOSTED_SD_PWR_CTRL_LDO_INTERNAL_IO
int "LDO ID"
default 4 if IDF_TARGET_ESP32P4
help
Please check your schematic first and input your LDO ID.
choice
prompt "SDIO Bus Width"
default ESP_HOSTED_SDIO_4_BIT_BUS
help
Select the SDIO Bus Width to use
config ESP_HOSTED_SDIO_4_BIT_BUS
bool "4 Bits"
config ESP_HOSTED_SDIO_1_BIT_BUS
bool "1 Bit"
endchoice
config ESP_HOSTED_SDIO_BUS_WIDTH
int
default 1 if ESP_HOSTED_SDIO_1_BIT_BUS
default 4
ESP32_SDIO_CLK_FREQ_KHZ_RANGE_MIN := 400
ESP32_SDIO_CLK_FREQ_KHZ_RANGE_MAX := 40000
ESP32XX_SDIO_CLK_FREQ_KHZ_RANGE_MIN := 400
ESP32XX_SDIO_CLK_FREQ_KHZ_RANGE_MAX := 50000
config ESP_HOSTED_SDIO_CLOCK_FREQ_KHZ
int "SDIO Clock Freq (in kHz)"
default 40000
range $(ESP32_SDIO_CLK_FREQ_KHZ_RANGE_MIN) $(ESP32_SDIO_CLK_FREQ_KHZ_RANGE_MAX) if IDF_TARGET_ESP32
range $(ESP32XX_SDIO_CLK_FREQ_KHZ_RANGE_MIN) $(ESP32XX_SDIO_CLK_FREQ_KHZ_RANGE_MAX) if IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32P4
help
"Optimize SDIO CLK by increasing till host practically can support. Clock frequency for ESP32-P4 as host <= 40MHz"
config ESP_HOSTED_SDIO_CMD_GPIO_RANGE_MIN
int
default 51 if ESP_HOSTED_P4_C5_CORE_BOARD
default 52 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 27 if ESP32P4_EYE_C6_BOARD
default 13 if ESP32P4_TAB5_C6_BOARD
default 19 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 4 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 19 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 15 if IDF_TARGET_ESP32
default 0
config ESP_HOSTED_SDIO_CMD_GPIO_RANGE_MAX
int
default 51 if ESP_HOSTED_P4_C5_CORE_BOARD
default 52 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 27 if ESP32P4_EYE_C6_BOARD
default 13 if ESP32P4_TAB5_C6_BOARD
default 19 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 4 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 19 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 15 if IDF_TARGET_ESP32
default 100
config ESP_HOSTED_SDIO_CLK_GPIO_RANGE_MIN
int
default 50 if ESP_HOSTED_P4_C5_CORE_BOARD
default 51 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 28 if ESP32P4_EYE_C6_BOARD
default 12 if ESP32P4_TAB5_C6_BOARD
default 18 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 33 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 18 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 14 if IDF_TARGET_ESP32
default 0
config ESP_HOSTED_SDIO_CLK_GPIO_RANGE_MAX
int
default 50 if ESP_HOSTED_P4_C5_CORE_BOARD
default 51 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 28 if ESP32P4_EYE_C6_BOARD
default 12 if ESP32P4_TAB5_C6_BOARD
default 18 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 33 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 18 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 14 if IDF_TARGET_ESP32
default 100
config ESP_HOSTED_SDIO_D0_GPIO_RANGE_MIN
int
default 49 if ESP_HOSTED_P4_C5_CORE_BOARD
default 50 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 29 if ESP32P4_EYE_C6_BOARD
default 11 if ESP32P4_TAB5_C6_BOARD
default 14 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 20 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 14 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 2 if IDF_TARGET_ESP32
default 0
config ESP_HOSTED_SDIO_D0_GPIO_RANGE_MAX
int
default 49 if ESP_HOSTED_P4_C5_CORE_BOARD
default 50 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 29 if ESP32P4_EYE_C6_BOARD
default 11 if ESP32P4_TAB5_C6_BOARD
default 14 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 20 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 14 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 2 if IDF_TARGET_ESP32
default 100
config ESP_HOSTED_SDIO_D1_GPIO_RANGE_MIN
int
default 48 if ESP_HOSTED_P4_C5_CORE_BOARD
default 49 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 30 if ESP32P4_EYE_C6_BOARD
default 10 if ESP32P4_TAB5_C6_BOARD
default 15 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 23 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 15 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 4 if IDF_TARGET_ESP32
default 0
config ESP_HOSTED_SDIO_D1_GPIO_RANGE_MAX
int
default 48 if ESP_HOSTED_P4_C5_CORE_BOARD
default 49 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 30 if ESP32P4_EYE_C6_BOARD
default 10 if ESP32P4_TAB5_C6_BOARD
default 15 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 23 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 15 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 4 if IDF_TARGET_ESP32
default 100
config ESP_HOSTED_SDIO_D2_GPIO_RANGE_MIN
int
default 53 if ESP_HOSTED_P4_C5_CORE_BOARD
default 48 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 31 if ESP32P4_EYE_C6_BOARD
default 9 if ESP32P4_TAB5_C6_BOARD
default 16 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 21 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 16 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 12 if IDF_TARGET_ESP32
default 0
config ESP_HOSTED_SDIO_D2_GPIO_RANGE_MAX
int
default 53 if ESP_HOSTED_P4_C5_CORE_BOARD
default 48 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 31 if ESP32P4_EYE_C6_BOARD
default 9 if ESP32P4_TAB5_C6_BOARD
default 16 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 21 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 16 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 12 if IDF_TARGET_ESP32
default 100
config ESP_HOSTED_SDIO_D3_GPIO_RANGE_MIN
int
default 52 if ESP_HOSTED_P4_C5_CORE_BOARD
default 47 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 32 if ESP32P4_EYE_C6_BOARD
default 8 if ESP32P4_TAB5_C6_BOARD
default 17 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 22 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 17 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 13 if IDF_TARGET_ESP32
default 0
config ESP_HOSTED_SDIO_D3_GPIO_RANGE_MAX
int
default 52 if ESP_HOSTED_P4_C5_CORE_BOARD
default 47 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 32 if ESP32P4_EYE_C6_BOARD
default 8 if ESP32P4_TAB5_C6_BOARD
default 17 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 22 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 17 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 13 if IDF_TARGET_ESP32
default 100
config ESP_HOSTED_SDIO_RESET_SLAVE_GPIO_MIN
int
default 54 if ESP_HOSTED_P4_C5_CORE_BOARD || ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 9 if ESP32P4_EYE_C6_BOARD
default 15 if ESP32P4_TAB5_C6_BOARD
default 54 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 53 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 54 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 5 if IDF_TARGET_ESP32
default 0
help
GPIO pin for Resetting ESP SDIO slave device. Should be connected to RST/EN of ESP SDIO slave device.
config ESP_HOSTED_SDIO_RESET_SLAVE_GPIO_MAX
int
default 9 if ESP32P4_EYE_C6_BOARD
default 15 if ESP32P4_TAB5_C6_BOARD
default 54 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C6
default 53 if ESP_HOSTED_P4_DEV_BOARD_FUNC_BOARD && ESP_HOSTED_CP_TARGET_ESP32C5
default 54 if ESP_HOSTED_P4X_C5_DEV_BOARD_FUNC_BOARD
default 5 if IDF_TARGET_ESP32
default 100
### *START* GPIO SDIO pin configurations for Slot 0 and 1
config ESP_HOSTED_PRIV_SDIO_PIN_CMD_SLOT_0
depends on ESP_HOSTED_SDIO_SLOT_0
int "CMD GPIO number"
default 47 if IDF_TARGET_ESP32S3
range 44 44 if IDF_TARGET_ESP32P4
range 15 15 if IDF_TARGET_ESP32
help
"Value can only be configured for some targets. Displayed always for reference."
config ESP_HOSTED_PRIV_SDIO_PIN_CMD_SLOT_1
depends on ESP_HOSTED_SDIO_SLOT_1
int "CMD GPIO number"
default 47 if IDF_TARGET_ESP32S3
default 51 if ESP_HOSTED_P4_C5_CORE_BOARD
default 52 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 27 if ESP32P4_EYE_C6_BOARD
default 13 if ESP32P4_TAB5_C6_BOARD
default 19 if IDF_TARGET_ESP32P4
default 15 if IDF_TARGET_ESP32
range ESP_HOSTED_SDIO_CMD_GPIO_RANGE_MIN ESP_HOSTED_SDIO_CMD_GPIO_RANGE_MAX
help
CMD GPIO pin for SDIO. Range enforced dynamically based on slave target to ensure IOMUX compliance.
config ESP_HOSTED_PRIV_SDIO_PIN_CLK_SLOT_0
depends on ESP_HOSTED_SDIO_SLOT_0
int "CLK GPIO number"
default 19 if IDF_TARGET_ESP32S3
range 43 43 if IDF_TARGET_ESP32P4
range 14 14 if IDF_TARGET_ESP32
help
"Value can only be configured for some targets. Displayed always for reference."
config ESP_HOSTED_PRIV_SDIO_PIN_CLK_SLOT_1
depends on ESP_HOSTED_SDIO_SLOT_1
int "CLK GPIO number"
default 19 if IDF_TARGET_ESP32S3
default 50 if ESP_HOSTED_P4_C5_CORE_BOARD
default 51 if ESP_HOSTED_P4_C6_CORE_BOARD || ESP_HOSTED_P4_C61_CORE_BOARD
default 28 if ESP32P4_EYE_C6_BOARD
default 12 if ESP32P4_TAB5_C6_BOARD
default 18 if IDF_TARGET_ESP32P4
default 14 if IDF_TARGET_ESP32
range ESP_HOSTED_SDIO_CLK_GPIO_RANGE_MIN ESP_HOSTED_SDIO_CLK_GPIO_RANGE_MAX
help
CLK GPIO pin for SDIO. Range enforced dynamically based on slave target to ensure IOMUX compliance.
config ESP_HOSTED_PRIV_SDIO_PIN_D0_SLOT_0
depends on ESP_HOSTED_SDIO_SLOT_0
int "D0 GPIO number"