1616from pathlib import Path
1717
1818
19+ def has_tle_pass (pass_name : Optional [str ] = None ) -> bool :
20+ tle_passes = getattr (iluvatar .passes , "tle" , None )
21+ if tle_passes is None :
22+ return False
23+ if pass_name is None :
24+ return True
25+ return hasattr (tle_passes , pass_name )
26+
27+
1928def min_dot_size (target : GPUTarget ):
2029
2130 def check_dot_compatibility (lhs_type , rhs_type ) -> Tuple [int , int , int ]: # [m, n, k]
@@ -106,7 +115,7 @@ def sm_arch_from_capability(capability: int):
106115
107116
108117@dataclass (frozen = True )
109- class CUDAOptions :
118+ class CorexOptions :
110119 num_warps : int = 4
111120 num_ctas : int = 1
112121 num_stages : int = 3
@@ -121,7 +130,9 @@ class CUDAOptions:
121130 enable_reflect_ftz : bool = True # ftz in libdevice
122131 launch_cooperative_grid : bool = False
123132 launch_pdl : bool = False
124- supported_fp8_dtypes : Tuple [str ] = ("fp8e5" , "fp8e4b15" )
133+ # OCP only: fp8e5 always; fp8e4nv added for sm71 (ivcore11 SW) / sm89+.
134+ # fp8e4b15 is NVIDIA PTX-asm software format — not supported on Iluvatar.
135+ supported_fp8_dtypes : Tuple [str ] = ("fp8e5" , )
125136 deprecated_fp8_dot_operand_dtypes : Tuple [str ] = ()
126137 default_dot_input_precision : str = "tf32"
127138 allowed_dot_input_precisions : Tuple [str ] = ("tf32" , "tf32x3" , "ieee" , 'bf16x3' , 'bf16x6' )
@@ -152,12 +163,12 @@ def hash(self):
152163 return hashlib .sha256 (key .encode ("utf-8" )).hexdigest ()
153164
154165
155- class CUDABackend (BaseBackend ):
166+ class CorexBackend (BaseBackend ):
156167 instrumentation = None
157168
158169 @staticmethod
159170 def supports_target (target : GPUTarget ):
160- return target .backend == 'corex'
171+ return target .backend in ( 'corex' , 'cuda' )
161172
162173 def _parse_arch (self , arch ):
163174 pattern = r"^sm(\d+)$"
@@ -171,6 +182,8 @@ def get_target_name(self, options) -> str:
171182 return f"cuda:{ capability } "
172183
173184 def __init__ (self , target : GPUTarget ) -> None :
185+ if target .backend == 'cuda' :
186+ target = GPUTarget ('corex' , target .arch , target .warp_size )
174187 super ().__init__ (target )
175188 self .binary_ext = "cubin"
176189
@@ -180,7 +193,7 @@ def parse_options(self, opts) -> Any:
180193 opts ["debug" ] = True
181194
182195 args = {'arch' : knobs .runtime .override_arch or f"sm{ self .target .arch } " }
183- args .update ({k : opts [k ] for k in CUDAOptions .__dataclass_fields__ .keys () if k in opts if opts [k ] is not None })
196+ args .update ({k : opts [k ] for k in CorexOptions .__dataclass_fields__ .keys () if k in opts if opts [k ] is not None })
184197 capability = int (self ._parse_arch (args ["arch" ]))
185198
186199 if args .get ("num_ctas" , 1 ) > 1 and capability < 90 :
@@ -189,21 +202,18 @@ def parse_options(self, opts) -> Any:
189202 f"Please set num_ctas=1 or target an SM90+ GPU." ))
190203
191204 if "supported_fp8_dtypes" not in args :
192- supported_fp8_dtypes = set (CUDAOptions .supported_fp8_dtypes )
193- if capability >= 89 :
205+ supported_fp8_dtypes = set (CorexOptions .supported_fp8_dtypes )
206+ # ivcore11 (sm71): software FP8; ivcore30 will use native HW when mapped.
207+ if capability >= 89 or capability == 71 :
194208 supported_fp8_dtypes .add ("fp8e4nv" )
195209 args ["supported_fp8_dtypes" ] = tuple (sorted (supported_fp8_dtypes ))
196210
197- if "deprecated_fp8_dot_operand_dtypes" not in args :
198- if capability >= 90 :
199- args ["deprecated_fp8_dot_operand_dtypes" ] = ("fp8e4b15" , )
200-
201211 if "enable_fp_fusion" not in args :
202212 args ["enable_fp_fusion" ] = knobs .language .default_fp_fusion
203213
204214 args ["max_num_imprecise_acc_default" ] = 2 ** 30 if capability == 90 else 0
205215
206- return CUDAOptions (** args )
216+ return CorexOptions (** args )
207217
208218 def pack_metadata (self , metadata ):
209219 return (
@@ -228,8 +238,8 @@ def get_module_map(self) -> Dict[str, ModuleType]:
228238
229239 def load_dialects (self , ctx ):
230240 iluvatar .load_dialects (ctx )
231- if CUDABackend .instrumentation :
232- CUDABackend .instrumentation .load_dialects (ctx )
241+ if CorexBackend .instrumentation :
242+ CorexBackend .instrumentation .load_dialects (ctx )
233243
234244 @staticmethod
235245 def make_ttir (mod , metadata , opt , capability ):
@@ -263,15 +273,26 @@ def make_ttgir(mod, metadata, opt, capability):
263273 passes .ttgpuir .add_f32_dot_tc (pm , emuTF32 )
264274 passes .ttgpuir .add_remove_layout_conversions (pm )
265275 passes .ttgpuir .add_optimize_thread_locality (pm )
266- if hasattr (iluvatar .passes , "tle" ):
276+ if has_tle_pass ():
277+ if has_tle_pass ("add_optimize_local_pointer_async_stores" ):
278+ iluvatar .passes .tle .add_optimize_local_pointer_async_stores (pm )
279+ if has_tle_pass ("add_early_assign_memory_space" ):
280+ iluvatar .passes .tle .add_early_assign_memory_space (pm )
281+ if has_tle_pass ("add_optimize_exclusive_cumsum_layouts" ):
282+ iluvatar .passes .tle .add_optimize_exclusive_cumsum_layouts (pm )
283+ if has_tle_pass ("add_lower_exclusive_cumsum" ):
284+ iluvatar .passes .tle .add_lower_exclusive_cumsum (pm )
267285 iluvatar .passes .tle .add_insert_local_pointer_barriers (pm )
268286 iluvatar .passes .tle .add_optimize_local_pointer_loads (pm )
269287 iluvatar .passes .tle .add_optimize_local_pointer_stores (pm )
288+ if has_tle_pass ("add_lower_pipe_to_barriers" ):
289+ iluvatar .passes .tle .add_lower_pipe_to_barriers (pm )
270290 iluvatar .passes .ttgpuir .add_accelerate_matmul (pm , opt .use_sme )
271291 passes .ttgpuir .add_remove_layout_conversions (pm )
272292 iluvatar .passes .ttgpuir .add_mma_reduce_thread_locality (pm )
273293 iluvatar .passes .ttgpuir .add_optimize_epilogue (pm )
274294 passes .ttgpuir .add_optimize_dot_operands (pm , capability >= 71 )
295+ iluvatar .passes .ttgpuir .add_matmul_smeload (pm , capability )
275296 passes .ttir .add_loop_aware_cse (pm )
276297 if capability // 10 in [7 , 8 , 9 ]:
277298 passes .ttgpuir .add_fuse_nested_loops (pm )
@@ -281,6 +302,7 @@ def make_ttgir(mod, metadata, opt, capability):
281302 passes .ttgpuir .add_combine_tensor_select_and_if (pm )
282303 passes .ttgpuir .add_assign_latencies (pm , opt .num_stages )
283304 passes .ttgpuir .add_schedule_loops (pm )
305+ passes .ttgpuir .add_pipeline (pm , opt .num_stages , dump_enabled )
284306 elif capability // 10 >= 10 :
285307 passes .ttgpuir .add_fuse_nested_loops (pm )
286308 passes .common .add_canonicalizer (pm )
@@ -299,10 +321,11 @@ def make_ttgir(mod, metadata, opt, capability):
299321 passes .ttir .add_triton_licm (pm )
300322 passes .common .add_canonicalizer (pm )
301323 passes .ttir .add_loop_aware_cse (pm )
302- iluvatar .passes .ttgpuir .add_matmul_smeload (pm , capability )
303324 passes .ttgpuir .add_remove_layout_conversions (pm )
304325 passes .ttgpuir .add_prefetch (pm )
305326 passes .ttgpuir .add_optimize_dot_operands (pm , capability >= 71 )
327+ if has_tle_pass ("add_lower_async_load" ):
328+ iluvatar .passes .tle .add_lower_async_load (pm )
306329 passes .ttgpuir .add_coalesce_async_copy (pm )
307330 passes .ttgpuir .add_remove_layout_conversions (pm )
308331 passes .ttgpuir .add_reduce_data_duplication (pm )
@@ -350,12 +373,15 @@ def make_llir(self, src, metadata, options, capability):
350373 # Call ConcurrencySanitizerPass here, before allocating global scratch memory but after allocating tensor and shared
351374 passes .ttgpuir .add_concurrency_sanitizer (pm )
352375 passes .ttgpuir .add_allocate_global_scratch_memory (pm )
353- if CUDABackend .instrumentation :
354- CUDABackend .instrumentation .patch ("ttgpuir_to_llvmir" , pm , mod .context )
376+ if CorexBackend .instrumentation :
377+ CorexBackend .instrumentation .patch ("ttgpuir_to_llvmir" , pm , mod .context )
355378 proc = sm_arch_from_capability (capability )
356379 iluvatar .passes .ttgpuir .add_to_llvmir (pm , proc , options .enable_reflect_ftz )
357380 passes .common .add_canonicalizer (pm )
358381 passes .common .add_cse (pm )
382+ # [WA] On ivcore11 this relies on a shared-memory software barrier
383+ # because the architecture lacks hardware named barriers and setmaxnreg.
384+ iluvatar .passes .ttgpuir .add_warp_specialize_to_llvm (pm , proc )
359385 passes .common .add_canonicalizer (pm )
360386 passes .common .add_cse (pm )
361387 passes .common .add_symbol_dce (pm )
@@ -364,8 +390,8 @@ def make_llir(self, src, metadata, options, capability):
364390 if not knobs .compilation .disable_line_info and not knobs .compilation .dump_ir_extract_di_local_variables :
365391 passes .llvmir .add_di_scope (pm )
366392
367- if CUDABackend .instrumentation :
368- CUDABackend .instrumentation .patch ("llvmir_to_llvm" , pm , mod .context )
393+ if CorexBackend .instrumentation :
394+ CorexBackend .instrumentation .patch ("llvmir_to_llvm" , pm , mod .context )
369395
370396 pm .run (mod , 'make_llir' )
371397
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