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sync the tsingmicro backend patches
1 parent c016f71 commit f4a4406

131 files changed

Lines changed: 11164 additions & 3177 deletions

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@@ -1 +1,2 @@
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add_subdirectory(tle-dsa/Dialect/IR)
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third_party/tle/include/tle-dsa/Dialect/IR/CMakeLists.txt

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@@ -12,3 +12,4 @@ set(LLVM_TARGET_DEFINITIONS DsaOps.td)
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mlir_tablegen(DsaOps.h.inc -gen-op-decls)
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mlir_tablegen(DsaOps.cpp.inc -gen-op-defs)
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add_public_tablegen_target(TleDsaOpsIncGen)
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third_party/tle/include/tle-dsa/Dialect/IR/DsaDialect.h

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@@ -15,8 +15,8 @@
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// DsaOps.td uses TT_Tensor / TT_Ptr / TT_Int type constraints from the
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// Triton dialect, so the generated verifiers need these types visible.
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#include "triton/Dialect/Triton/IR/Dialect.h"
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#include "triton/Dialect/Triton/IR/Types.h"
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#include "triton/Dialect/Triton/IR/Dialect.h"
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#include "tle-dsa/Dialect/IR/DsaOpsDialect.h.inc"
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@@ -31,3 +31,4 @@ class PatternRewriter;
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#include "tle-dsa/Dialect/IR/DsaOps.h.inc"
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#endif // TLE_DSA_DIALECT_IR_DSADIALECT_H
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third_party/tle/include/tle-dsa/Dialect/IR/DsaDialect.td

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@@ -66,3 +66,4 @@ class Dsa_Op<string mnemonic, list<Trait> traits = []> :
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Op<Dsa_Dialect, mnemonic, traits>;
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#endif // TLE_DSA_DIALECT
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third_party/tle/include/tle-dsa/Dialect/IR/DsaOps.td

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@@ -72,8 +72,31 @@ def Dsa_DistributedBarrierOp : Dsa_Op<"distributed_barrier",
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def Dsa_RemotePointersOp : Dsa_Op<"remote_pointers", [Pure]> {
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let arguments = (ins DsaRemotePointerType:$src, DsaRemoteShardIdType:$shard_id,
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OptionalAttr<DenseI32ArrayAttr>:$mesh_physical_ids);
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OptionalAttr<DenseI32ArrayAttr>:$mesh_physical_ids,
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OptionalAttr<DenseI32ArrayAttr>:$mesh_shape);
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let results = (outs DsaRemotePointerType:$result);
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}
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def DsaCumsumInputType : RankedTensorOf<[TT_Float, TT_Int]>;
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def DsaCumsumTotalResultType : AnyTypeOf<[DsaCumsumInputType, TT_Float, TT_Int]>;
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//===----------------------------------------------------------------------===//
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// dsa.cumsum
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//===----------------------------------------------------------------------===//
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def Dsa_CumsumOp : Dsa_Op<"cumsum", [Pure]> {
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let summary = "exclusive cumsum marker lowered by Tsingmicro CRT";
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let arguments = (ins
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DsaCumsumInputType:$input,
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I32Attr:$axis,
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BoolAttr:$reverse,
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DenseI64ArrayAttr:$shape,
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I64Attr:$pad
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);
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let results = (outs
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DsaCumsumInputType:$exclusive,
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DsaCumsumTotalResultType:$total
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);
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}
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#endif // TLE_DSA_OPS

third_party/tle/lib/CMakeLists.txt

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@@ -1,2 +1,3 @@
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add_subdirectory(Dialect/IR)
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add_subdirectory(Conversion/DsaToCore)
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third_party/tle/lib/Conversion/DsaToCore/DsaToCore.cpp

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@@ -26,7 +26,8 @@ struct DsaAllocToMemRefPattern : public OpRewritePattern<mlir::dsa::AllocOp> {
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return failure();
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// tx81-memref-to-llvm expects integer/default memref address spaces.
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// Canonicalize away non-integer memory-space attrs (e.g. "local").
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if (Attribute ms = memrefTy.getMemorySpace(); ms && !isa<IntegerAttr>(ms)) {
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if (Attribute ms = memrefTy.getMemorySpace();
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ms && !isa<IntegerAttr>(ms)) {
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memrefTy = MemRefType::get(memrefTy.getShape(), memrefTy.getElementType(),
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memrefTy.getLayout());
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}
@@ -56,7 +57,8 @@ struct DsaMemoryToCorePass
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RewritePatternSet patterns(&getContext());
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patterns.add<DsaAllocToMemRefPattern, DsaCopyToMemRefPattern>(
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&getContext());
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if (failed(applyPatternsGreedily(getOperation(), std::move(patterns))))
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if (failed(applyPatternsGreedily(getOperation(),
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std::move(patterns))))
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signalPassFailure();
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}
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};

third_party/tle/lib/Dialect/IR/CMakeLists.txt

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@@ -17,3 +17,4 @@ target_include_directories(TleDsaIR
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${TLE_INCLUDE_SOURCE}
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${TLE_INCLUDE_BINARY}
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)
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third_party/tle/lib/Dialect/IR/DsaDialect.cpp

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@@ -37,3 +37,4 @@ void DsaDialect::registerTypes() {
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#define GET_TYPEDEF_CLASSES
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#include "tle-dsa/Dialect/IR/DsaOpsTypes.cpp.inc"
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third_party/tle/python/CMakeLists.txt

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@@ -5,3 +5,4 @@ if(TRITON_BUILD_PYTHON_MODULE)
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)
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target_link_libraries(TritonTleDsaTemplate PRIVATE Python3::Module pybind11::headers)
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endif()
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