Clarification of How to Properly Set Timings?

[lupinthird]

Hello!

For those of us with the capabilities to measure clock signals/timings etc with an oscilloscope -- would it be possible to explain what actual o-scope timings correlate to what timing patch values? Is there a formula? I mean something that lays it out in a FAQ would be really helpful. If your Phi2 = X then the first timing parameter should be Y, etc.

I'm really just looking for some solid advice about how to "know" what timings should be used, as I feel like I'm really struggling with a lot of guesswork, which is annoying since I have all of the tools at my disposal to look under the hood in detail.

Thanks for creating the only real viable aftermarket solution for replacement SIDs!
lupinthird

[modeler]

I thought about this also, but the range of possible values is not sufficiently granular to warrant busting out an o-scope, in my opinion. The SKpicotiming tool is a big help, so if I find that SKP is glitching in the board I just make small adjustments until it resolves, then patch the firmware.

[modeler]

Although long boards seem to be very picky about the bus timings while short boards tend to "just work", one thing I have noticed is that the optimal values seem to be tied to the CPU itself.

For example, I have a breadbin that is very picky, I have to set the timings to like READBUS=7, PHI2=6 to eliminate all the glitches, but if I swap out the 6510 for an 8500 it works just fine using the default timings. Not sure if the TTL vs. CMOS logic makes a difference here?