main.stanza

; Generated by JITX 3.31.2
#use-added-syntax(jitx)
defpackage main :
  import core
  import jitx
  import jitx/commands
  import jitx/parts

  import helpers
  import jsl

; Define the shape/size of the board
val board-shape = RoundedRectangle(30.0, 18.5, 0.25)

; Module to run as a design
pcb-module my-design :
  ; define some case-sensitive pins/ports
  port gnd
  port vdd
  port signal

  ; Create nets for the pins/ports which will be used to connect component pins 
  ; Note that the net names are case-sensitive as well.
  net GND (gnd)
  net VDD (vdd)
  net SIGNAL (signal)

  ; Instantiate and connect a 10k resistor component between the named nets VDD and SIGNAL
  insert-resistor(VDD, SIGNAL, R-query, resistance = 10.0e3)
  ; Instantiate and connect a 100nF capacitor component between the named nets VDD and GND
  insert-capacitor(VDD, GND, C-query, capacitance = 100.0e-9)

  ; Attach schematic symbols to the nets (from JSL)
  symbol(GND) = GND-SYMB
  symbol(VDD) = PWR-SYMB

; Set the :
;     design-name     - a directory with this name will be created in the "designs" directory
;     board           - a Board object representing the stackup, rules and board shape for a particular design
;     signal-shrink   - a distance in mm to pull back copper signals from the board edge
setup-design("jitx-design", board-shape, signal-shrink = 0.5)

; Set the top level module (the module to be compile into a schematic and PCB)
set-main-module(my-design)

; View the results
; take a look at the BOM that was generated
view-bom(BOM-STD)
; examine the schematic that was auto-generated
view-schematic()
; view the board that was created
view-board()