kbootloader/aarch64: replace broken PIE loader with self-contained Rynux-style boot (#45)

* Initial plan

* Refactor kbootloader: implement Rynux-style PIE kernel boot for AArch64

Co-authored-by: guoweikang <18571063+guoweikang@users.noreply.github.com>

---------

Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
Co-authored-by: guoweikang <18571063+guoweikang@users.noreply.github.com>

Author: Copilot

platforms/kbootloader/Cargo.toml

@@ -16,6 +16,7 @@ macros = { workspace = true }
 # Architecture-specific dependencies
 [target.'cfg(target_arch = "aarch64")'.dependencies]
 aarch64-cpu = "10.0"
-aarch64-cpu-ext = "0.1"
-kasm-aarch64 = {workspace = true}
-smccc = "0.2"
+karch = { workspace = true }
+page_table = { workspace = true }
+memaddr = { workspace = true }
+kplat = { workspace = true, features = ["smp"] }

platforms/kbootloader/build.rs

@@ -1,5 +1,9 @@
 use std::{env, fs, path::PathBuf};
 
+fn out_dir() -> PathBuf {
+    PathBuf::from(env::var("OUT_DIR").unwrap())
+}
+
 fn main() {
     let arch = env::var("CARGO_CFG_TARGET_ARCH").unwrap();
 
@@ -13,7 +17,7 @@ fn main() {
         println!("cargo::rustc-cfg=hard_float");
     }
 
-    let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
+    let out_dir = out_dir();
 
     // Read linker script template
     let linker_script_src =

platforms/kbootloader/linker.lds.S

@@ -1,6 +1,7 @@
 OUTPUT_ARCH(%ARCH%)
 
-BASE_ADDRESS = %KERNEL_IMAGE_VADDR%;
+PAGE_SIZE = 0x1000;
+BASE_ADDRESS = %KERNEL_BASE%;
 
 SECTIONS
 {
@@ -39,12 +40,6 @@ SECTIONS
         __init_array_end = .;
     }
 
-    .boot_loader : ALIGN(PAGE_SIZE) {
-        __boot_loader_start = .;
-        KEEP(*(.boot_loader))
-        __boot_loader_end = .;
-    }
-
     .data : ALIGN(4K) {
         _erodata = .;
         _sdata = .;
@@ -113,9 +108,3 @@ SECTIONS
         *(.comment) *(.gnu*) *(.note*) *(.eh_frame*)
     }
 }
-
-EXTERN(__pie_boot_default_secondary);
-EXTERN(__somehal_handle_irq_default);
-
-PROVIDE(__pie_boot_secondary = __pie_boot_default_secondary);
-PROVIDE(__somehal_handle_irq = __somehal_handle_irq_default);

platforms/kbootloader/src/arch/aarch64/el.rs

@@ -1,100 +1,57 @@
-use core::arch::asm;
+// SPDX-License-Identifier: Apache-2.0
+// Copyright 2025 KylinSoft Co., Ltd. <https://www.kylinos.cn/>
+// See LICENSES for license details.
+
+//! AArch64 exception level switching for early boot.
 
 use aarch64_cpu::{asm::barrier, registers::*};
-use aarch64_cpu_ext::asm::tlb::{VAAE1IS, VMALLE1, tlbi};
-use page_table_generic::VirtAddr;
-use crate::start_code;
-use crate::mem::PageTable;
 
+/// Switch from EL3/EL2 down to EL1.
+///
+/// Must be called before the MMU is enabled. All addresses are physical.
+///
+/// # Safety
+///
+/// Changes the CPU exception level. Must only be called once during early boot.
 #[unsafe(link_section = ".idmap.text")]
-pub fn switch_to_elx(bootargs: usize) {
+pub unsafe fn switch_to_el1() {
     SPSel.write(SPSel::SP::ELx);
     SP_EL0.set(0);
     let current_el = CurrentEL.read(CurrentEL::EL);
-    let ret = sym_lma!(super::_start_secondary);
     if current_el >= 2 {
         if current_el == 3 {
-            // Set EL2 to 64bit and enable the HVC instruction.
+            // Set EL2 to 64-bit and enable the HVC instruction.
             SCR_EL3.write(
-                SCR_EL3::NS::NonSecure + SCR_EL3::HCE::HvcEnabled + SCR_EL3::RW::NextELIsAarch64,
+                SCR_EL3::NS::NonSecure
+                    + SCR_EL3::HCE::HvcEnabled
+                    + SCR_EL3::RW::NextELIsAarch64,
             );
-            // Set the return address and exception level.
+            // Return to EL1h.
             SPSR_EL3.write(
                 SPSR_EL3::M::EL1h
                     + SPSR_EL3::D::Masked
                     + SPSR_EL3::A::Masked
                     + SPSR_EL3::I::Masked
                     + SPSR_EL3::F::Masked,
             );
-
-            ELR_EL3.set(ret as _);
-            barrier::isb(barrier::SY);
-            unsafe {
-                asm!(
-                    "
-                    mov x0, {}
-                    eret
-                    ",
-                    in(reg) bootargs,
-                    options(nostack, noreturn),
-                );
-            }
+            ELR_EL3.set(LR.get());
         }
-        // Disable EL1 timer traps and the timer offset.
+        // Disable EL1 timer traps and clear the timer offset.
         CNTHCTL_EL2.modify(CNTHCTL_EL2::EL1PCEN::SET + CNTHCTL_EL2::EL1PCTEN::SET);
         CNTVOFF_EL2.set(0);
-        // Set EL1 to 64bit.
+        // Set EL1 to 64-bit.
         HCR_EL2.write(HCR_EL2::RW::EL1IsAarch64);
-        // Set the return address and exception level.
+        // Return to EL1h.
         SPSR_EL2.write(
             SPSR_EL2::M::EL1h
                 + SPSR_EL2::D::Masked
                 + SPSR_EL2::A::Masked
                 + SPSR_EL2::I::Masked
                 + SPSR_EL2::F::Masked,
         );
-
-        unsafe {
-            ELR_EL2.set(ret as _);
-            barrier::isb(barrier::SY);
-
-            asm!(
-                "
-            mov x0, {}
-            eret
-            ",
-                in(reg) bootargs,
-                options(nostack, noreturn),
-            )
-        };
-    }
-}
-
-#[inline(always)]
-pub(crate) fn flush_tlb(vaddr: Option<VirtAddr>) {
-    match vaddr {
-        Some(addr) => {
-            tlbi(VAAE1IS::new(addr.raw()));
-        }
-        None => {
-            tlbi(VMALLE1);
-        }
+        SP_EL1.set(SP.get());
+        ELR_EL2.set(LR.get());
+        barrier::isb(barrier::SY);
+        aarch64_cpu::asm::eret();
     }
-    barrier::dsb(barrier::SY);
-    barrier::isb(barrier::SY);
-}
-
-pub fn get_kernal_table() -> PageTable {
-    let val = TTBR1_EL1.extract();
-    PageTable {
-        id: val.read(TTBR1_EL1::ASID) as _,
-        addr: (val.read(TTBR1_EL1::BADDR) << 1) as _,
-    }
-}
-
-pub fn set_kernal_table(tb: PageTable) {
-    TTBR1_EL1.set(TTBR1_EL1::ASID.val(tb.id as u64).value + tb.addr as u64);
-    tlbi(VMALLE1);
-    barrier::dsb(barrier::SY);
-    barrier::isb(barrier::SY);
 }