fix(vol4): fix table math delimiters in 04-nervous, 08-perception, 13-placement

Author: profvjreddi

books/vol4/chapters/04-nervous/04-nervous.qmd

@@ -313,12 +313,12 @@ Real-time dependability cannot be achieved by buying faster clock speeds or meas
 ![](figures/fig04_real_industrial_ethercat_controller.jpg){width="85%"}
 :::
 
-| Interconnect Protocol                                        | Physical Topology & Signaling                                            | Payload Throughput ($\beta$)                                                        | Transfer Latency & Cycle Jitter                                                                                       | Determinism Classification                                  | Physical Reach & Wiring Harness                                                            | Physical AI Subsystem Placement                                               |
-|:-------------------------------------------------------------|:-------------------------------------------------------------------------|:------------------------------------------------------------------------------------|:----------------------------------------------------------------------------------------------------------------------|:------------------------------------------------------------|:-------------------------------------------------------------------------------------------|:------------------------------------------------------------------------------|
-| **SPI** (Serial Peripheral Interface)                        | Synchronous 4-wire full-duplex (SCLK, MOSI, MISO, CS), point-to-point    | $10\text{--}50\text{ Mbps}$ (up to $80\text{ Mbps}$ in QSPI/OSPI)                   | Latency: $0.5\text{--}2.0\,\mu\text{s}$ \newline Jitter: $< 50\text{ ns}$                                             | **Bounded** (cycle-deterministic register reads)            | $< 0.3\text{ m}$ (intra-board PCB traces / flat flex)                                      | Joint magnetic angle encoders, 3-phase current-sense ADCs, gate drivers       |
-| **CAN-FD** (Controller Area Network FD)                      | 2-wire differential multidrop with bitwise priority arbitration          | $1\text{ Mbps}$ arbitration, $5\text{--}8\text{ Mbps}$ data phase (64-byte payload) | Latency: $$25\text{--}150\,\mu\text{s}$$ \newline Jitter: $$$10\text{--}50\,\mu\text{s}$$                             | **Analytically Bounded** (strictly bounded for top IDs)     | $\le 40\text{ m}$ at $1\text{ Mbps}$ / $\le 15\text{ m}$ at $5\text{ Mbps}$ (twisted pair) | Chassis management, battery management systems (BMS), auxiliary actuators     |
-| **EtherCAT** (Ethernet Control Automation)                   | 100BASE-TX full-duplex daisy-chain; on-the-fly hardware frame processing | $100\text{ Mbps}$ ($1\text{ Gbps}$ in EtherCAT G), payload efficiency $>90\%$       | Latency: $1.0\text{--}5.0\,\mu\text{s}$ per node \newline Jitter: $< 100\text{ ns}$ (distributed clocks)              | **Hard Real-Time** (hardware-scheduled cyclic PDO frames)   | $\le 100\text{ m}$ between nodes (shielded Cat5e/Cat6)                                     | Multi-axis robot arm joint servos, high-rate force-torque sensors             |
-| **TSN Ethernet** (IEEE 802.1Qbv / Time-Sensitive Networking) | Star/mesh switched Ethernet with time-aware traffic shapers              | $1\text{--}10\text{ Gbps}$ full-duplex                                              | Latency: $$$10\text{--}50\,\mu\text{s}$$ (scheduled slots) \newline Jitter: $< 1.0\,\mu\text{s}$ (PTP / IEEE 802.1AS) | **Scheduled Deterministic** (time-gated queue transmission) | $\le 100\text{ m}$ per link                                                                | Centralized backbone bridging multi-camera vision, lidar, and safety reflexes |
+| Interconnect Protocol                                        | Physical Topology & Signaling                                            | Payload Throughput ($\beta$)                                                        | Transfer Latency & Cycle Jitter                                                                                    | Determinism Classification                                  | Physical Reach & Wiring Harness                                                            | Physical AI Subsystem Placement                                               |
+|:-------------------------------------------------------------|:-------------------------------------------------------------------------|:------------------------------------------------------------------------------------|:-------------------------------------------------------------------------------------------------------------------|:------------------------------------------------------------|:-------------------------------------------------------------------------------------------|:------------------------------------------------------------------------------|
+| **SPI** (Serial Peripheral Interface)                        | Synchronous 4-wire full-duplex (SCLK, MOSI, MISO, CS), point-to-point    | $10\text{--}50\text{ Mbps}$ (up to $80\text{ Mbps}$ in QSPI/OSPI)                   | Latency: $0.5\text{--}2.0\,\mu\text{s}$ \newline Jitter: $< 50\text{ ns}$                                          | **Bounded** (cycle-deterministic register reads)            | $< 0.3\text{ m}$ (intra-board PCB traces / flat flex)                                      | Joint magnetic angle encoders, 3-phase current-sense ADCs, gate drivers       |
+| **CAN-FD** (Controller Area Network FD)                      | 2-wire differential multidrop with bitwise priority arbitration          | $1\text{ Mbps}$ arbitration, $5\text{--}8\text{ Mbps}$ data phase (64-byte payload) | Latency: $25\text{--}150\,\mu\text{s}$ \newline Jitter: $10\text{--}50\,\mu\text{s}$                               | **Analytically Bounded** (strictly bounded for top IDs)     | $\le 40\text{ m}$ at $1\text{ Mbps}$ / $\le 15\text{ m}$ at $5\text{ Mbps}$ (twisted pair) | Chassis management, battery management systems (BMS), auxiliary actuators     |
+| **EtherCAT** (Ethernet Control Automation)                   | 100BASE-TX full-duplex daisy-chain; on-the-fly hardware frame processing | $100\text{ Mbps}$ ($1\text{ Gbps}$ in EtherCAT G), payload efficiency $>90\%$       | Latency: $1.0\text{--}5.0\,\mu\text{s}$ per node \newline Jitter: $< 100\text{ ns}$ (distributed clocks)           | **Hard Real-Time** (hardware-scheduled cyclic PDO frames)   | $\le 100\text{ m}$ between nodes (shielded Cat5e/Cat6)                                     | Multi-axis robot arm joint servos, high-rate force-torque sensors             |
+| **TSN Ethernet** (IEEE 802.1Qbv / Time-Sensitive Networking) | Star/mesh switched Ethernet with time-aware traffic shapers              | $1\text{--}10\text{ Gbps}$ full-duplex                                              | Latency: $10\text{--}50\,\mu\text{s}$ (scheduled slots) \newline Jitter: $< 1.0\,\mu\text{s}$ (PTP / IEEE 802.1AS) | **Scheduled Deterministic** (time-gated queue transmission) | $\le 100\text{ m}$ per link                                                                | Centralized backbone bridging multi-camera vision, lidar, and safety reflexes |
 : **Fieldbus and Interconnect Protocol Trade-Off Matrix for Physical AI Subsystems**: Comparative breakdown of physical signaling, bandwidth, transfer latency, cycle jitter, determinism classification, physical reach, and canonical subsystem placement across robotics interconnects. SPI provides sub-microsecond register access within a single board; CAN-FD provides robust priority-arbitrated messaging across chassis wiring; EtherCAT delivers microsecond-level hardware cycle synchronization across distributed joint motor drives; and TSN Ethernet unifies high-bandwidth vision streams with scheduled real-time control frames over a single physical backbone. {#tbl-04-fieldbus-comparison}
 
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