This project is to down sample a 256*256 image to 128*128 image.
Here we have several process to decide before implementing the code.
- Develop a suitable downsapling algorithm in matlab and simulate it.
- Design ISA considering the algorithm we developed and its main funtionalities.
- Design the state machine,required registers,data paths etc.
- Implement the code with assembly according to the ISA we have developed.
- Create a test bench simulate it for error free processor.
- UART link to upload and retrieve image from FPGA.
- Test with real time images and debugging for 0 SSD.
Date : 2018.06.22 Project : Semester 5 group project Authers: Isuru Nuwanthilaka,Chirath Diyagama,Chandula Nethmal,Dileepa Perera