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Copy pathAVR64DU32def.inc
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6287 lines (5621 loc) · 341 KB
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;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : AVR64DU32def.inc
;* Title : Register/Bit Definitions for the AVR64DU32
;* Created : 2023-12-12 10:24
;* Version : 1.00
;* Support : https://microchipsupport.force.com/
;* Target MCU : AVR64DU32
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;*************************************************************************
#ifndef _AVR64DU32DEF_INC_
#define _AVR64DU32DEF_INC_
#pragma partinc 0
; ***** SPECIFY DEVICE ***************************************************
.device AVR64DU32
#pragma AVRPART ADMIN PART_NAME AVR64DU32
.equ SIGNATURE_000 = 0x1E
.equ SIGNATURE_001 = 0x96
.equ SIGNATURE_002 = 0x21
#pragma AVRPART CORE CORE_VERSION V4S
.equ USB_MAX_ENDPOINTS = 16
; ***** ABSOLUTE I/O REGISTER LOCATIONS **********************************
;*************************************************************************
;** AC0 - Analog Comparator
;*************************************************************************
.equ AC0_CTRLA = 0x0680 ; Control A
.equ AC0_MUXCTRL = 0x0682 ; Mux Control A
.equ AC0_DACREF = 0x0685 ; DAC Voltage Reference
.equ AC0_INTCTRL = 0x0686 ; Interrupt Control
.equ AC0_STATUS = 0x0687 ; Status
;*************************************************************************
;** ADC0 - Analog to Digital Converter
;*************************************************************************
.equ ADC0_CTRLA = 0x0600 ; Control A
.equ ADC0_CTRLB = 0x0601 ; Control C
.equ ADC0_CTRLC = 0x0602 ; Control B
.equ ADC0_CTRLD = 0x0603 ; Control E
.equ ADC0_CTRLE = 0x0604 ; Control F
.equ ADC0_CTRLF = 0x0605 ; Control D
.equ ADC0_INTCTRL = 0x0606 ; Interrupt Control
.equ ADC0_INTFLAGS = 0x0607 ; Interrupt Flags
.equ ADC0_STATUS = 0x0608 ; Status
.equ ADC0_DBGCTRL = 0x0609 ; Debug Control
.equ ADC0_COMMAND = 0x060A ; Command
.equ ADC0_MUXPOS = 0x060B ; Positive mux input
.equ ADC0_RESULT = 0x060C ; ADC Accumulator Result
.equ ADC0_RESULTL = 0x060C ; ADC Accumulator Result low byte
.equ ADC0_RESULTH = 0x060D ; ADC Accumulator Result hi byte
.equ ADC0_SAMPLE = 0x060E ; ADC Sample
.equ ADC0_SAMPLEL = 0x060E ; ADC Sample low byte
.equ ADC0_SAMPLEH = 0x060F ; ADC Sample hi byte
.equ ADC0_WINLT = 0x0610 ; Window comparator low threshold
.equ ADC0_WINLTL = 0x0610 ; Window comparator low threshold low byte
.equ ADC0_WINLTH = 0x0611 ; Window comparator low threshold hi byte
.equ ADC0_WINHT = 0x0612 ; Window comparator high threshold
.equ ADC0_WINHTL = 0x0612 ; Window comparator high threshold low byte
.equ ADC0_WINHTH = 0x0613 ; Window comparator high threshold hi byte
.equ ADC0_TEMP = 0x0614 ; Temporary Data
;*************************************************************************
;** BOD - Bod interface
;*************************************************************************
.equ BOD_CTRLA = 0x00A0 ; Control A
.equ BOD_CTRLB = 0x00A1 ; Control B
.equ BOD_VLMCTRLA = 0x00A8 ; Voltage level monitor Control
.equ BOD_INTCTRL = 0x00A9 ; Voltage level monitor interrupt Control
.equ BOD_INTFLAGS = 0x00AA ; Voltage level monitor interrupt Flags
.equ BOD_STATUS = 0x00AB ; Voltage level monitor status
;*************************************************************************
;** BOOTROW - Boot Row
;*************************************************************************
.equ BOOTROW_BOOTROW0 = 0x1100 ; Boot row 0
.equ BOOTROW_BOOTROW1 = 0x1101 ; Boot row 1
.equ BOOTROW_BOOTROW2 = 0x1102 ; Boot row 2
.equ BOOTROW_BOOTROW3 = 0x1103 ; Boot row 3
.equ BOOTROW_BOOTROW4 = 0x1104 ; Boot row 4
.equ BOOTROW_BOOTROW5 = 0x1105 ; Boot row 5
.equ BOOTROW_BOOTROW6 = 0x1106 ; Boot row 6
.equ BOOTROW_BOOTROW7 = 0x1107 ; Boot row 7
.equ BOOTROW_BOOTROW8 = 0x1108 ; Boot row 8
.equ BOOTROW_BOOTROW9 = 0x1109 ; Boot row 9
.equ BOOTROW_BOOTROW10 = 0x110A ; Boot row 10
.equ BOOTROW_BOOTROW11 = 0x110B ; Boot row 11
.equ BOOTROW_BOOTROW12 = 0x110C ; Boot row 12
.equ BOOTROW_BOOTROW13 = 0x110D ; Boot row 13
.equ BOOTROW_BOOTROW14 = 0x110E ; Boot row 14
.equ BOOTROW_BOOTROW15 = 0x110F ; Boot row 15
.equ BOOTROW_BOOTROW16 = 0x1110 ; Boot row 16
.equ BOOTROW_BOOTROW17 = 0x1111 ; Boot row 17
.equ BOOTROW_BOOTROW18 = 0x1112 ; Boot row 18
.equ BOOTROW_BOOTROW19 = 0x1113 ; Boot row 19
.equ BOOTROW_BOOTROW20 = 0x1114 ; Boot row 20
.equ BOOTROW_BOOTROW21 = 0x1115 ; Boot row 21
.equ BOOTROW_BOOTROW22 = 0x1116 ; Boot row 22
.equ BOOTROW_BOOTROW23 = 0x1117 ; Boot row 23
.equ BOOTROW_BOOTROW24 = 0x1118 ; Boot row 24
.equ BOOTROW_BOOTROW25 = 0x1119 ; Boot row 25
.equ BOOTROW_BOOTROW26 = 0x111A ; Boot row 26
.equ BOOTROW_BOOTROW27 = 0x111B ; Boot row 27
.equ BOOTROW_BOOTROW28 = 0x111C ; Boot row 28
.equ BOOTROW_BOOTROW29 = 0x111D ; Boot row 29
.equ BOOTROW_BOOTROW30 = 0x111E ; Boot row 30
.equ BOOTROW_BOOTROW31 = 0x111F ; Boot row 31
.equ BOOTROW_BOOTROW32 = 0x1120 ; Boot row 32
.equ BOOTROW_BOOTROW33 = 0x1121 ; Boot row 33
.equ BOOTROW_BOOTROW34 = 0x1122 ; Boot row 34
.equ BOOTROW_BOOTROW35 = 0x1123 ; Boot row 35
.equ BOOTROW_BOOTROW36 = 0x1124 ; Boot row 36
.equ BOOTROW_BOOTROW37 = 0x1125 ; Boot row 37
.equ BOOTROW_BOOTROW38 = 0x1126 ; Boot row 38
.equ BOOTROW_BOOTROW39 = 0x1127 ; Boot row 39
.equ BOOTROW_BOOTROW40 = 0x1128 ; Boot row 40
.equ BOOTROW_BOOTROW41 = 0x1129 ; Boot row 41
.equ BOOTROW_BOOTROW42 = 0x112A ; Boot row 42
.equ BOOTROW_BOOTROW43 = 0x112B ; Boot row 43
.equ BOOTROW_BOOTROW44 = 0x112C ; Boot row 44
.equ BOOTROW_BOOTROW45 = 0x112D ; Boot row 45
.equ BOOTROW_BOOTROW46 = 0x112E ; Boot row 46
.equ BOOTROW_BOOTROW47 = 0x112F ; Boot row 47
.equ BOOTROW_BOOTROW48 = 0x1130 ; Boot row 48
.equ BOOTROW_BOOTROW49 = 0x1131 ; Boot row 49
.equ BOOTROW_BOOTROW50 = 0x1132 ; Boot row 50
.equ BOOTROW_BOOTROW51 = 0x1133 ; Boot row 51
.equ BOOTROW_BOOTROW52 = 0x1134 ; Boot row 52
.equ BOOTROW_BOOTROW53 = 0x1135 ; Boot row 53
.equ BOOTROW_BOOTROW54 = 0x1136 ; Boot row 54
.equ BOOTROW_BOOTROW55 = 0x1137 ; Boot row 55
.equ BOOTROW_BOOTROW56 = 0x1138 ; Boot row 56
.equ BOOTROW_BOOTROW57 = 0x1139 ; Boot row 57
.equ BOOTROW_BOOTROW58 = 0x113A ; Boot row 58
.equ BOOTROW_BOOTROW59 = 0x113B ; Boot row 59
.equ BOOTROW_BOOTROW60 = 0x113C ; Boot row 60
.equ BOOTROW_BOOTROW61 = 0x113D ; Boot row 61
.equ BOOTROW_BOOTROW62 = 0x113E ; Boot row 62
.equ BOOTROW_BOOTROW63 = 0x113F ; Boot row 63
.equ BOOTROW_BOOTROW64 = 0x1140 ; Boot row 64
.equ BOOTROW_BOOTROW65 = 0x1141 ; Boot row 65
.equ BOOTROW_BOOTROW66 = 0x1142 ; Boot row 66
.equ BOOTROW_BOOTROW67 = 0x1143 ; Boot row 67
.equ BOOTROW_BOOTROW68 = 0x1144 ; Boot row 68
.equ BOOTROW_BOOTROW69 = 0x1145 ; Boot row 69
.equ BOOTROW_BOOTROW70 = 0x1146 ; Boot row 70
.equ BOOTROW_BOOTROW71 = 0x1147 ; Boot row 71
.equ BOOTROW_BOOTROW72 = 0x1148 ; Boot row 72
.equ BOOTROW_BOOTROW73 = 0x1149 ; Boot row 73
.equ BOOTROW_BOOTROW74 = 0x114A ; Boot row 74
.equ BOOTROW_BOOTROW75 = 0x114B ; Boot row 75
.equ BOOTROW_BOOTROW76 = 0x114C ; Boot row 76
.equ BOOTROW_BOOTROW77 = 0x114D ; Boot row 77
.equ BOOTROW_BOOTROW78 = 0x114E ; Boot row 78
.equ BOOTROW_BOOTROW79 = 0x114F ; Boot row 79
.equ BOOTROW_BOOTROW80 = 0x1150 ; Boot row 80
.equ BOOTROW_BOOTROW81 = 0x1151 ; Boot row 81
.equ BOOTROW_BOOTROW82 = 0x1152 ; Boot row 82
.equ BOOTROW_BOOTROW83 = 0x1153 ; Boot row 83
.equ BOOTROW_BOOTROW84 = 0x1154 ; Boot row 84
.equ BOOTROW_BOOTROW85 = 0x1155 ; Boot row 85
.equ BOOTROW_BOOTROW86 = 0x1156 ; Boot row 86
.equ BOOTROW_BOOTROW87 = 0x1157 ; Boot row 87
.equ BOOTROW_BOOTROW88 = 0x1158 ; Boot row 88
.equ BOOTROW_BOOTROW89 = 0x1159 ; Boot row 89
.equ BOOTROW_BOOTROW90 = 0x115A ; Boot row 90
.equ BOOTROW_BOOTROW91 = 0x115B ; Boot row 91
.equ BOOTROW_BOOTROW92 = 0x115C ; Boot row 92
.equ BOOTROW_BOOTROW93 = 0x115D ; Boot row 93
.equ BOOTROW_BOOTROW94 = 0x115E ; Boot row 94
.equ BOOTROW_BOOTROW95 = 0x115F ; Boot row 95
.equ BOOTROW_BOOTROW96 = 0x1160 ; Boot row 96
.equ BOOTROW_BOOTROW97 = 0x1161 ; Boot row 97
.equ BOOTROW_BOOTROW98 = 0x1162 ; Boot row 98
.equ BOOTROW_BOOTROW99 = 0x1163 ; Boot row 99
.equ BOOTROW_BOOTROW100 = 0x1164 ; Boot row 100
.equ BOOTROW_BOOTROW101 = 0x1165 ; Boot row 101
.equ BOOTROW_BOOTROW102 = 0x1166 ; Boot row 102
.equ BOOTROW_BOOTROW103 = 0x1167 ; Boot row 103
.equ BOOTROW_BOOTROW104 = 0x1168 ; Boot row 104
.equ BOOTROW_BOOTROW105 = 0x1169 ; Boot row 105
.equ BOOTROW_BOOTROW106 = 0x116A ; Boot row 106
.equ BOOTROW_BOOTROW107 = 0x116B ; Boot row 107
.equ BOOTROW_BOOTROW108 = 0x116C ; Boot row 108
.equ BOOTROW_BOOTROW109 = 0x116D ; Boot row 109
.equ BOOTROW_BOOTROW110 = 0x116E ; Boot row 110
.equ BOOTROW_BOOTROW111 = 0x116F ; Boot row 111
.equ BOOTROW_BOOTROW112 = 0x1170 ; Boot row 112
.equ BOOTROW_BOOTROW113 = 0x1171 ; Boot row 113
.equ BOOTROW_BOOTROW114 = 0x1172 ; Boot row 114
.equ BOOTROW_BOOTROW115 = 0x1173 ; Boot row 115
.equ BOOTROW_BOOTROW116 = 0x1174 ; Boot row 116
.equ BOOTROW_BOOTROW117 = 0x1175 ; Boot row 117
.equ BOOTROW_BOOTROW118 = 0x1176 ; Boot row 118
.equ BOOTROW_BOOTROW119 = 0x1177 ; Boot row 119
.equ BOOTROW_BOOTROW120 = 0x1178 ; Boot row 120
.equ BOOTROW_BOOTROW121 = 0x1179 ; Boot row 121
.equ BOOTROW_BOOTROW122 = 0x117A ; Boot row 122
.equ BOOTROW_BOOTROW123 = 0x117B ; Boot row 123
.equ BOOTROW_BOOTROW124 = 0x117C ; Boot row 124
.equ BOOTROW_BOOTROW125 = 0x117D ; Boot row 125
.equ BOOTROW_BOOTROW126 = 0x117E ; Boot row 126
.equ BOOTROW_BOOTROW127 = 0x117F ; Boot row 127
.equ BOOTROW_BOOTROW128 = 0x1180 ; Boot row 128
.equ BOOTROW_BOOTROW129 = 0x1181 ; Boot row 129
.equ BOOTROW_BOOTROW130 = 0x1182 ; Boot row 130
.equ BOOTROW_BOOTROW131 = 0x1183 ; Boot row 131
.equ BOOTROW_BOOTROW132 = 0x1184 ; Boot row 132
.equ BOOTROW_BOOTROW133 = 0x1185 ; Boot row 133
.equ BOOTROW_BOOTROW134 = 0x1186 ; Boot row 134
.equ BOOTROW_BOOTROW135 = 0x1187 ; Boot row 135
.equ BOOTROW_BOOTROW136 = 0x1188 ; Boot row 136
.equ BOOTROW_BOOTROW137 = 0x1189 ; Boot row 137
.equ BOOTROW_BOOTROW138 = 0x118A ; Boot row 138
.equ BOOTROW_BOOTROW139 = 0x118B ; Boot row 139
.equ BOOTROW_BOOTROW140 = 0x118C ; Boot row 140
.equ BOOTROW_BOOTROW141 = 0x118D ; Boot row 141
.equ BOOTROW_BOOTROW142 = 0x118E ; Boot row 142
.equ BOOTROW_BOOTROW143 = 0x118F ; Boot row 143
.equ BOOTROW_BOOTROW144 = 0x1190 ; Boot row 144
.equ BOOTROW_BOOTROW145 = 0x1191 ; Boot row 145
.equ BOOTROW_BOOTROW146 = 0x1192 ; Boot row 146
.equ BOOTROW_BOOTROW147 = 0x1193 ; Boot row 147
.equ BOOTROW_BOOTROW148 = 0x1194 ; Boot row 148
.equ BOOTROW_BOOTROW149 = 0x1195 ; Boot row 149
.equ BOOTROW_BOOTROW150 = 0x1196 ; Boot row 150
.equ BOOTROW_BOOTROW151 = 0x1197 ; Boot row 151
.equ BOOTROW_BOOTROW152 = 0x1198 ; Boot row 152
.equ BOOTROW_BOOTROW153 = 0x1199 ; Boot row 153
.equ BOOTROW_BOOTROW154 = 0x119A ; Boot row 154
.equ BOOTROW_BOOTROW155 = 0x119B ; Boot row 155
.equ BOOTROW_BOOTROW156 = 0x119C ; Boot row 156
.equ BOOTROW_BOOTROW157 = 0x119D ; Boot row 157
.equ BOOTROW_BOOTROW158 = 0x119E ; Boot row 158
.equ BOOTROW_BOOTROW159 = 0x119F ; Boot row 159
.equ BOOTROW_BOOTROW160 = 0x11A0 ; Boot row 160
.equ BOOTROW_BOOTROW161 = 0x11A1 ; Boot row 161
.equ BOOTROW_BOOTROW162 = 0x11A2 ; Boot row 162
.equ BOOTROW_BOOTROW163 = 0x11A3 ; Boot row 163
.equ BOOTROW_BOOTROW164 = 0x11A4 ; Boot row 164
.equ BOOTROW_BOOTROW165 = 0x11A5 ; Boot row 165
.equ BOOTROW_BOOTROW166 = 0x11A6 ; Boot row 166
.equ BOOTROW_BOOTROW167 = 0x11A7 ; Boot row 167
.equ BOOTROW_BOOTROW168 = 0x11A8 ; Boot row 168
.equ BOOTROW_BOOTROW169 = 0x11A9 ; Boot row 169
.equ BOOTROW_BOOTROW170 = 0x11AA ; Boot row 170
.equ BOOTROW_BOOTROW171 = 0x11AB ; Boot row 171
.equ BOOTROW_BOOTROW172 = 0x11AC ; Boot row 172
.equ BOOTROW_BOOTROW173 = 0x11AD ; Boot row 173
.equ BOOTROW_BOOTROW174 = 0x11AE ; Boot row 174
.equ BOOTROW_BOOTROW175 = 0x11AF ; Boot row 175
.equ BOOTROW_BOOTROW176 = 0x11B0 ; Boot row 176
.equ BOOTROW_BOOTROW177 = 0x11B1 ; Boot row 177
.equ BOOTROW_BOOTROW178 = 0x11B2 ; Boot row 178
.equ BOOTROW_BOOTROW179 = 0x11B3 ; Boot row 179
.equ BOOTROW_BOOTROW180 = 0x11B4 ; Boot row 180
.equ BOOTROW_BOOTROW181 = 0x11B5 ; Boot row 181
.equ BOOTROW_BOOTROW182 = 0x11B6 ; Boot row 182
.equ BOOTROW_BOOTROW183 = 0x11B7 ; Boot row 183
.equ BOOTROW_BOOTROW184 = 0x11B8 ; Boot row 184
.equ BOOTROW_BOOTROW185 = 0x11B9 ; Boot row 185
.equ BOOTROW_BOOTROW186 = 0x11BA ; Boot row 186
.equ BOOTROW_BOOTROW187 = 0x11BB ; Boot row 187
.equ BOOTROW_BOOTROW188 = 0x11BC ; Boot row 188
.equ BOOTROW_BOOTROW189 = 0x11BD ; Boot row 189
.equ BOOTROW_BOOTROW190 = 0x11BE ; Boot row 190
.equ BOOTROW_BOOTROW191 = 0x11BF ; Boot row 191
.equ BOOTROW_BOOTROW192 = 0x11C0 ; Boot row 192
.equ BOOTROW_BOOTROW193 = 0x11C1 ; Boot row 193
.equ BOOTROW_BOOTROW194 = 0x11C2 ; Boot row 194
.equ BOOTROW_BOOTROW195 = 0x11C3 ; Boot row 195
.equ BOOTROW_BOOTROW196 = 0x11C4 ; Boot row 196
.equ BOOTROW_BOOTROW197 = 0x11C5 ; Boot row 197
.equ BOOTROW_BOOTROW198 = 0x11C6 ; Boot row 198
.equ BOOTROW_BOOTROW199 = 0x11C7 ; Boot row 199
.equ BOOTROW_BOOTROW200 = 0x11C8 ; Boot row 200
.equ BOOTROW_BOOTROW201 = 0x11C9 ; Boot row 201
.equ BOOTROW_BOOTROW202 = 0x11CA ; Boot row 202
.equ BOOTROW_BOOTROW203 = 0x11CB ; Boot row 203
.equ BOOTROW_BOOTROW204 = 0x11CC ; Boot row 204
.equ BOOTROW_BOOTROW205 = 0x11CD ; Boot row 205
.equ BOOTROW_BOOTROW206 = 0x11CE ; Boot row 206
.equ BOOTROW_BOOTROW207 = 0x11CF ; Boot row 207
.equ BOOTROW_BOOTROW208 = 0x11D0 ; Boot row 208
.equ BOOTROW_BOOTROW209 = 0x11D1 ; Boot row 209
.equ BOOTROW_BOOTROW210 = 0x11D2 ; Boot row 210
.equ BOOTROW_BOOTROW211 = 0x11D3 ; Boot row 211
.equ BOOTROW_BOOTROW212 = 0x11D4 ; Boot row 212
.equ BOOTROW_BOOTROW213 = 0x11D5 ; Boot row 213
.equ BOOTROW_BOOTROW214 = 0x11D6 ; Boot row 214
.equ BOOTROW_BOOTROW215 = 0x11D7 ; Boot row 215
.equ BOOTROW_BOOTROW216 = 0x11D8 ; Boot row 216
.equ BOOTROW_BOOTROW217 = 0x11D9 ; Boot row 217
.equ BOOTROW_BOOTROW218 = 0x11DA ; Boot row 218
.equ BOOTROW_BOOTROW219 = 0x11DB ; Boot row 219
.equ BOOTROW_BOOTROW220 = 0x11DC ; Boot row 220
.equ BOOTROW_BOOTROW221 = 0x11DD ; Boot row 221
.equ BOOTROW_BOOTROW222 = 0x11DE ; Boot row 222
.equ BOOTROW_BOOTROW223 = 0x11DF ; Boot row 223
.equ BOOTROW_BOOTROW224 = 0x11E0 ; Boot row 224
.equ BOOTROW_BOOTROW225 = 0x11E1 ; Boot row 225
.equ BOOTROW_BOOTROW226 = 0x11E2 ; Boot row 226
.equ BOOTROW_BOOTROW227 = 0x11E3 ; Boot row 227
.equ BOOTROW_BOOTROW228 = 0x11E4 ; Boot row 228
.equ BOOTROW_BOOTROW229 = 0x11E5 ; Boot row 229
.equ BOOTROW_BOOTROW230 = 0x11E6 ; Boot row 230
.equ BOOTROW_BOOTROW231 = 0x11E7 ; Boot row 231
.equ BOOTROW_BOOTROW232 = 0x11E8 ; Boot row 232
.equ BOOTROW_BOOTROW233 = 0x11E9 ; Boot row 233
.equ BOOTROW_BOOTROW234 = 0x11EA ; Boot row 234
.equ BOOTROW_BOOTROW235 = 0x11EB ; Boot row 235
.equ BOOTROW_BOOTROW236 = 0x11EC ; Boot row 236
.equ BOOTROW_BOOTROW237 = 0x11ED ; Boot row 237
.equ BOOTROW_BOOTROW238 = 0x11EE ; Boot row 238
.equ BOOTROW_BOOTROW239 = 0x11EF ; Boot row 239
.equ BOOTROW_BOOTROW240 = 0x11F0 ; Boot row 240
.equ BOOTROW_BOOTROW241 = 0x11F1 ; Boot row 241
.equ BOOTROW_BOOTROW242 = 0x11F2 ; Boot row 242
.equ BOOTROW_BOOTROW243 = 0x11F3 ; Boot row 243
.equ BOOTROW_BOOTROW244 = 0x11F4 ; Boot row 244
.equ BOOTROW_BOOTROW245 = 0x11F5 ; Boot row 245
.equ BOOTROW_BOOTROW246 = 0x11F6 ; Boot row 246
.equ BOOTROW_BOOTROW247 = 0x11F7 ; Boot row 247
.equ BOOTROW_BOOTROW248 = 0x11F8 ; Boot row 248
.equ BOOTROW_BOOTROW249 = 0x11F9 ; Boot row 249
.equ BOOTROW_BOOTROW250 = 0x11FA ; Boot row 250
.equ BOOTROW_BOOTROW251 = 0x11FB ; Boot row 251
.equ BOOTROW_BOOTROW252 = 0x11FC ; Boot row 252
.equ BOOTROW_BOOTROW253 = 0x11FD ; Boot row 253
.equ BOOTROW_BOOTROW254 = 0x11FE ; Boot row 254
.equ BOOTROW_BOOTROW255 = 0x11FF ; Boot row 255
;*************************************************************************
;** CCL - Configurable Custom Logic
;*************************************************************************
.equ CCL_CTRLA = 0x01C0 ; Control Register A
.equ CCL_SEQCTRL0 = 0x01C1 ; Sequential Control 0
.equ CCL_SEQCTRL1 = 0x01C2 ; Sequential Control 1
.equ CCL_INTCTRL0 = 0x01C5 ; Interrupt Control 0
.equ CCL_INTFLAGS = 0x01C7 ; Interrupt Flags
.equ CCL_LUT0CTRLA = 0x01C8 ; LUT 0 Control A
.equ CCL_LUT0CTRLB = 0x01C9 ; LUT 0 Control B
.equ CCL_LUT0CTRLC = 0x01CA ; LUT 0 Control C
.equ CCL_TRUTH0 = 0x01CB ; Truth 0
.equ CCL_LUT1CTRLA = 0x01CC ; LUT 1 Control A
.equ CCL_LUT1CTRLB = 0x01CD ; LUT 1 Control B
.equ CCL_LUT1CTRLC = 0x01CE ; LUT 1 Control C
.equ CCL_TRUTH1 = 0x01CF ; Truth 1
.equ CCL_LUT2CTRLA = 0x01D0 ; LUT 2 Control A
.equ CCL_LUT2CTRLB = 0x01D1 ; LUT 2 Control B
.equ CCL_LUT2CTRLC = 0x01D2 ; LUT 2 Control C
.equ CCL_TRUTH2 = 0x01D3 ; Truth 2
.equ CCL_LUT3CTRLA = 0x01D4 ; LUT 3 Control A
.equ CCL_LUT3CTRLB = 0x01D5 ; LUT 3 Control B
.equ CCL_LUT3CTRLC = 0x01D6 ; LUT 3 Control C
.equ CCL_TRUTH3 = 0x01D7 ; Truth 3
;*************************************************************************
;** CLKCTRL - Clock controller
;*************************************************************************
.equ CLKCTRL_MCLKCTRLA = 0x0060 ; MCLK Control A
.equ CLKCTRL_MCLKCTRLB = 0x0061 ; MCLK Control B
.equ CLKCTRL_MCLKCTRLC = 0x0062 ; MCLK Control C
.equ CLKCTRL_MCLKINTCTRL = 0x0063 ; MCLK Interrupt Control
.equ CLKCTRL_MCLKINTFLAGS = 0x0064 ; MCLK Interrupt Flags
.equ CLKCTRL_MCLKSTATUS = 0x0065 ; MCLK Status
.equ CLKCTRL_MCLKTIMEBASE = 0x0066 ; Timebase
.equ CLKCTRL_OSCHFCTRLA = 0x0068 ; OSCHF Control A
.equ CLKCTRL_OSCHFTUNE = 0x0069 ; OSCHF Tune
.equ CLKCTRL_OSCHFSTATUS = 0x006A ; OSCHF Status
.equ CLKCTRL_OSC32KCTRLA = 0x0078 ; OSC32K Control A
.equ CLKCTRL_XOSC32KCTRLA = 0x007C ; XOSC32K Control A
.equ CLKCTRL_XOSCHFCTRLA = 0x0080 ; XOSCHF Control A
.equ CLKCTRL_USBPLLSTATUS = 0x0085 ; PLL Status
;*************************************************************************
;** CPU - CPU
;*************************************************************************
.equ CPU_CCP = 0x0034 ; Configuration Change Protection
.equ CPU_RAMPZ = 0x003B ; Extended Z-pointer Register
.equ CPU_SP = 0x003D ; Stack Pointer
.equ CPU_SPL = 0x003D ; Stack Pointer low byte
.equ CPU_SPH = 0x003E ; Stack Pointer hi byte
.equ CPU_SREG = 0x003F ; Status Register
;*************************************************************************
;** CPUINT - Interrupt Controller
;*************************************************************************
.equ CPUINT_CTRLA = 0x0110 ; Control A
.equ CPUINT_STATUS = 0x0111 ; Status
.equ CPUINT_LVL0PRI = 0x0112 ; Interrupt Level 0 Priority
.equ CPUINT_LVL1VEC = 0x0113 ; Interrupt Level 1 Priority Vector
;*************************************************************************
;** CRCSCAN - CRCSCAN
;*************************************************************************
.equ CRCSCAN_CTRLA = 0x0120 ; Control A
.equ CRCSCAN_CTRLB = 0x0121 ; Control B
.equ CRCSCAN_STATUS = 0x0122 ; Status
;*************************************************************************
;** EVSYS - Event System
;*************************************************************************
.equ EVSYS_SWEVENTA = 0x0200 ; Software Event A
.equ EVSYS_CHANNEL0 = 0x0210 ; Multiplexer Channel 0
.equ EVSYS_CHANNEL1 = 0x0211 ; Multiplexer Channel 1
.equ EVSYS_CHANNEL2 = 0x0212 ; Multiplexer Channel 2
.equ EVSYS_CHANNEL3 = 0x0213 ; Multiplexer Channel 3
.equ EVSYS_CHANNEL4 = 0x0214 ; Multiplexer Channel 4
.equ EVSYS_CHANNEL5 = 0x0215 ; Multiplexer Channel 5
.equ EVSYS_USERCCLLUT0A = 0x0220 ; CCL0 Event A
.equ EVSYS_USERCCLLUT0B = 0x0221 ; CCL0 Event B
.equ EVSYS_USERCCLLUT1A = 0x0222 ; CCL1 Event A
.equ EVSYS_USERCCLLUT1B = 0x0223 ; CCL1 Event B
.equ EVSYS_USERCCLLUT2A = 0x0224 ; CCL2 Event A
.equ EVSYS_USERCCLLUT2B = 0x0225 ; CCL2 Event B
.equ EVSYS_USERCCLLUT3A = 0x0226 ; CCL3 Event A
.equ EVSYS_USERCCLLUT3B = 0x0227 ; CCL3 Event B
.equ EVSYS_USERADC0START = 0x0228 ; ADC0
.equ EVSYS_USEREVSYSEVOUTA = 0x0229 ; EVOUTA
.equ EVSYS_USEREVSYSEVOUTD = 0x022A ; EVOUTD
.equ EVSYS_USEREVSYSEVOUTF = 0x022B ; EVOUTF
.equ EVSYS_USERUSART0IRDA = 0x022C ; USART0
.equ EVSYS_USERUSART1IRDA = 0x022D ; USART1
.equ EVSYS_USERTCA0CNTA = 0x022E ; TCA0 Event A
.equ EVSYS_USERTCA0CNTB = 0x022F ; TCA0 Event B
.equ EVSYS_USERTCB0CAPT = 0x0230 ; TCB0 Event A
.equ EVSYS_USERTCB0COUNT = 0x0231 ; TCB0 Event B
.equ EVSYS_USERTCB1CAPT = 0x0232 ; TCB1 Event A
.equ EVSYS_USERTCB1COUNT = 0x0233 ; TCB1 Event B
;*************************************************************************
;** FUSE - Fuses
;*************************************************************************
.equ FUSE_WDTCFG = 0x1050 ; Watchdog Configuration
.equ FUSE_BODCFG = 0x1051 ; BOD Configuration
.equ FUSE_OSCCFG = 0x1052 ; Oscillator Configuration
.equ FUSE_SYSCFG0 = 0x1055 ; System Configuration 0
.equ FUSE_SYSCFG1 = 0x1056 ; System Configuration 1
.equ FUSE_CODESIZE = 0x1057 ; Code Section Size
.equ FUSE_BOOTSIZE = 0x1058 ; Boot Section Size
.equ FUSE_PDICFG = 0x105A ; Programming and Debugging Interface Configuration
.equ FUSE_PDICFGL = 0x105A ; Programming and Debugging Interface Configuration low byte
.equ FUSE_PDICFGH = 0x105B ; Programming and Debugging Interface Configuration hi byte
;*************************************************************************
;** GPR - General Purpose Registers
;*************************************************************************
.equ GPR_GPR0 = 0x001C ; General Purpose Register 0
.equ GPR_GPR1 = 0x001D ; General Purpose Register 1
.equ GPR_GPR2 = 0x001E ; General Purpose Register 2
.equ GPR_GPR3 = 0x001F ; General Purpose Register 3
;*************************************************************************
;** LOCK - Lockbits
;*************************************************************************
.equ LOCK_KEY = 0x1040 ; Lock Key Bits
.equ LOCK_KEY0 = 0x1040 ; Lock Key Bits 0
.equ LOCK_KEY1 = 0x1041 ; Lock Key Bits 1
.equ LOCK_KEY2 = 0x1042 ; Lock Key Bits 2
.equ LOCK_KEY3 = 0x1043 ; Lock Key Bits 3
;*************************************************************************
;** NVMCTRL - Non-volatile Memory Controller
;*************************************************************************
.equ NVMCTRL_CTRLA = 0x1000 ; Control A
.equ NVMCTRL_CTRLB = 0x1001 ; Control B
.equ NVMCTRL_CTRLC = 0x1002 ; Control C
.equ NVMCTRL_INTCTRL = 0x1004 ; Interrupt Control
.equ NVMCTRL_INTFLAGS = 0x1005 ; Interrupt Flags
.equ NVMCTRL_STATUS = 0x1006 ; Status
.equ NVMCTRL_DATA = 0x1008 ; Data
.equ NVMCTRL_DATA0 = 0x1008 ; Data 0
.equ NVMCTRL_DATA1 = 0x1009 ; Data 1
.equ NVMCTRL_DATA2 = 0x100A ; Data 2
.equ NVMCTRL_DATA3 = 0x100B ; Data 3
.equ NVMCTRL_ADDR = 0x100C ; Address
.equ NVMCTRL_ADDR0 = 0x100C ; Address 0
.equ NVMCTRL_ADDR1 = 0x100D ; Address 1
.equ NVMCTRL_ADDR2 = 0x100E ; Address 2
.equ NVMCTRL_ADDR3 = 0x100F ; Address 3
;*************************************************************************
;** PORTA - I/O Ports
;*************************************************************************
.equ PORTA_DIR = 0x0400 ; Data Direction
.equ PORTA_DIRSET = 0x0401 ; Data Direction Set
.equ PORTA_DIRCLR = 0x0402 ; Data Direction Clear
.equ PORTA_DIRTGL = 0x0403 ; Data Direction Toggle
.equ PORTA_OUT = 0x0404 ; Output Value
.equ PORTA_OUTSET = 0x0405 ; Output Value Set
.equ PORTA_OUTCLR = 0x0406 ; Output Value Clear
.equ PORTA_OUTTGL = 0x0407 ; Output Value Toggle
.equ PORTA_IN = 0x0408 ; Input Value
.equ PORTA_INTFLAGS = 0x0409 ; Interrupt Flags
.equ PORTA_PORTCTRL = 0x040A ; Port Control
.equ PORTA_PINCONFIG = 0x040B ; Pin Control Config
.equ PORTA_PINCTRLUPD = 0x040C ; Pin Control Update
.equ PORTA_PINCTRLSET = 0x040D ; Pin Control Set
.equ PORTA_PINCTRLCLR = 0x040E ; Pin Control Clear
.equ PORTA_PIN0CTRL = 0x0410 ; Pin 0 Control
.equ PORTA_PIN1CTRL = 0x0411 ; Pin 1 Control
.equ PORTA_PIN2CTRL = 0x0412 ; Pin 2 Control
.equ PORTA_PIN3CTRL = 0x0413 ; Pin 3 Control
.equ PORTA_PIN4CTRL = 0x0414 ; Pin 4 Control
.equ PORTA_PIN5CTRL = 0x0415 ; Pin 5 Control
.equ PORTA_PIN6CTRL = 0x0416 ; Pin 6 Control
.equ PORTA_PIN7CTRL = 0x0417 ; Pin 7 Control
.equ PORTA_EVGENCTRLA = 0x0418 ; Event Generation Control A
;*************************************************************************
;** PORTC - I/O Ports
;*************************************************************************
.equ PORTC_DIR = 0x0440 ; Data Direction
.equ PORTC_DIRSET = 0x0441 ; Data Direction Set
.equ PORTC_DIRCLR = 0x0442 ; Data Direction Clear
.equ PORTC_DIRTGL = 0x0443 ; Data Direction Toggle
.equ PORTC_OUT = 0x0444 ; Output Value
.equ PORTC_OUTSET = 0x0445 ; Output Value Set
.equ PORTC_OUTCLR = 0x0446 ; Output Value Clear
.equ PORTC_OUTTGL = 0x0447 ; Output Value Toggle
.equ PORTC_IN = 0x0448 ; Input Value
.equ PORTC_INTFLAGS = 0x0449 ; Interrupt Flags
.equ PORTC_PORTCTRL = 0x044A ; Port Control
.equ PORTC_PINCONFIG = 0x044B ; Pin Control Config
.equ PORTC_PINCTRLUPD = 0x044C ; Pin Control Update
.equ PORTC_PINCTRLSET = 0x044D ; Pin Control Set
.equ PORTC_PINCTRLCLR = 0x044E ; Pin Control Clear
.equ PORTC_PIN0CTRL = 0x0450 ; Pin 0 Control
.equ PORTC_PIN1CTRL = 0x0451 ; Pin 1 Control
.equ PORTC_PIN2CTRL = 0x0452 ; Pin 2 Control
.equ PORTC_PIN3CTRL = 0x0453 ; Pin 3 Control
.equ PORTC_PIN4CTRL = 0x0454 ; Pin 4 Control
.equ PORTC_PIN5CTRL = 0x0455 ; Pin 5 Control
.equ PORTC_PIN6CTRL = 0x0456 ; Pin 6 Control
.equ PORTC_PIN7CTRL = 0x0457 ; Pin 7 Control
.equ PORTC_EVGENCTRLA = 0x0458 ; Event Generation Control A
;*************************************************************************
;** PORTD - I/O Ports
;*************************************************************************
.equ PORTD_DIR = 0x0460 ; Data Direction
.equ PORTD_DIRSET = 0x0461 ; Data Direction Set
.equ PORTD_DIRCLR = 0x0462 ; Data Direction Clear
.equ PORTD_DIRTGL = 0x0463 ; Data Direction Toggle
.equ PORTD_OUT = 0x0464 ; Output Value
.equ PORTD_OUTSET = 0x0465 ; Output Value Set
.equ PORTD_OUTCLR = 0x0466 ; Output Value Clear
.equ PORTD_OUTTGL = 0x0467 ; Output Value Toggle
.equ PORTD_IN = 0x0468 ; Input Value
.equ PORTD_INTFLAGS = 0x0469 ; Interrupt Flags
.equ PORTD_PORTCTRL = 0x046A ; Port Control
.equ PORTD_PINCONFIG = 0x046B ; Pin Control Config
.equ PORTD_PINCTRLUPD = 0x046C ; Pin Control Update
.equ PORTD_PINCTRLSET = 0x046D ; Pin Control Set
.equ PORTD_PINCTRLCLR = 0x046E ; Pin Control Clear
.equ PORTD_PIN0CTRL = 0x0470 ; Pin 0 Control
.equ PORTD_PIN1CTRL = 0x0471 ; Pin 1 Control
.equ PORTD_PIN2CTRL = 0x0472 ; Pin 2 Control
.equ PORTD_PIN3CTRL = 0x0473 ; Pin 3 Control
.equ PORTD_PIN4CTRL = 0x0474 ; Pin 4 Control
.equ PORTD_PIN5CTRL = 0x0475 ; Pin 5 Control
.equ PORTD_PIN6CTRL = 0x0476 ; Pin 6 Control
.equ PORTD_PIN7CTRL = 0x0477 ; Pin 7 Control
.equ PORTD_EVGENCTRLA = 0x0478 ; Event Generation Control A
;*************************************************************************
;** PORTF - I/O Ports
;*************************************************************************
.equ PORTF_DIR = 0x04A0 ; Data Direction
.equ PORTF_DIRSET = 0x04A1 ; Data Direction Set
.equ PORTF_DIRCLR = 0x04A2 ; Data Direction Clear
.equ PORTF_DIRTGL = 0x04A3 ; Data Direction Toggle
.equ PORTF_OUT = 0x04A4 ; Output Value
.equ PORTF_OUTSET = 0x04A5 ; Output Value Set
.equ PORTF_OUTCLR = 0x04A6 ; Output Value Clear
.equ PORTF_OUTTGL = 0x04A7 ; Output Value Toggle
.equ PORTF_IN = 0x04A8 ; Input Value
.equ PORTF_INTFLAGS = 0x04A9 ; Interrupt Flags
.equ PORTF_PORTCTRL = 0x04AA ; Port Control
.equ PORTF_PINCONFIG = 0x04AB ; Pin Control Config
.equ PORTF_PINCTRLUPD = 0x04AC ; Pin Control Update
.equ PORTF_PINCTRLSET = 0x04AD ; Pin Control Set
.equ PORTF_PINCTRLCLR = 0x04AE ; Pin Control Clear
.equ PORTF_PIN0CTRL = 0x04B0 ; Pin 0 Control
.equ PORTF_PIN1CTRL = 0x04B1 ; Pin 1 Control
.equ PORTF_PIN2CTRL = 0x04B2 ; Pin 2 Control
.equ PORTF_PIN3CTRL = 0x04B3 ; Pin 3 Control
.equ PORTF_PIN4CTRL = 0x04B4 ; Pin 4 Control
.equ PORTF_PIN5CTRL = 0x04B5 ; Pin 5 Control
.equ PORTF_PIN6CTRL = 0x04B6 ; Pin 6 Control
.equ PORTF_PIN7CTRL = 0x04B7 ; Pin 7 Control
.equ PORTF_EVGENCTRLA = 0x04B8 ; Event Generation Control A
;*************************************************************************
;** PORTMUX - Port Multiplexer
;*************************************************************************
.equ PORTMUX_EVSYSROUTEA = 0x05E0 ; EVSYS route A
.equ PORTMUX_CCLROUTEA = 0x05E1 ; CCL route A
.equ PORTMUX_USARTROUTEA = 0x05E2 ; USART route A
.equ PORTMUX_SPIROUTEA = 0x05E5 ; SPI route A
.equ PORTMUX_TWIROUTEA = 0x05E6 ; TWI route A
.equ PORTMUX_TCAROUTEA = 0x05E7 ; TCA route A
.equ PORTMUX_TCBROUTEA = 0x05E8 ; TCB route A
;*************************************************************************
;** RSTCTRL - Reset controller
;*************************************************************************
.equ RSTCTRL_RSTFR = 0x0040 ; Reset Flags
.equ RSTCTRL_SWRR = 0x0041 ; Software Reset
;*************************************************************************
;** RTC - Real-Time Counter
;*************************************************************************
.equ RTC_CTRLA = 0x0140 ; Control A
.equ RTC_STATUS = 0x0141 ; Status
.equ RTC_INTCTRL = 0x0142 ; Interrupt Control
.equ RTC_INTFLAGS = 0x0143 ; Interrupt Flags
.equ RTC_TEMP = 0x0144 ; Temporary
.equ RTC_DBGCTRL = 0x0145 ; Debug control
.equ RTC_CALIB = 0x0146 ; Calibration
.equ RTC_CLKSEL = 0x0147 ; Clock Select
.equ RTC_CNT = 0x0148 ; Counter
.equ RTC_CNTL = 0x0148 ; Counter low byte
.equ RTC_CNTH = 0x0149 ; Counter hi byte
.equ RTC_PER = 0x014A ; Period
.equ RTC_PERL = 0x014A ; Period low byte
.equ RTC_PERH = 0x014B ; Period hi byte
.equ RTC_CMP = 0x014C ; Compare
.equ RTC_CMPL = 0x014C ; Compare low byte
.equ RTC_CMPH = 0x014D ; Compare hi byte
.equ RTC_PITCTRLA = 0x0150 ; PIT Control A
.equ RTC_PITSTATUS = 0x0151 ; PIT Status
.equ RTC_PITINTCTRL = 0x0152 ; PIT Interrupt Control
.equ RTC_PITINTFLAGS = 0x0153 ; PIT Interrupt Flags
.equ RTC_PITDBGCTRL = 0x0155 ; PIT Debug control
.equ RTC_PITEVGENCTRLA = 0x0156 ; PIT Event Generation Control A
;*************************************************************************
;** SIGROW - Signature row
;*************************************************************************
.equ SIGROW_DEVICEID0 = 0x1080 ; Device ID Byte 0
.equ SIGROW_DEVICEID1 = 0x1081 ; Device ID Byte 1
.equ SIGROW_DEVICEID2 = 0x1082 ; Device ID Byte 2
.equ SIGROW_TEMPSENSE0 = 0x1084 ; Temperature Calibration 0
.equ SIGROW_TEMPSENSE0L = 0x1084 ; Temperature Calibration 0 low byte
.equ SIGROW_TEMPSENSE0H = 0x1085 ; Temperature Calibration 0 hi byte
.equ SIGROW_TEMPSENSE1 = 0x1086 ; Temperature Calibration 1
.equ SIGROW_TEMPSENSE1L = 0x1086 ; Temperature Calibration 1 low byte
.equ SIGROW_TEMPSENSE1H = 0x1087 ; Temperature Calibration 1 hi byte
.equ SIGROW_SERNUM0 = 0x1090 ; LOTNUM0
.equ SIGROW_SERNUM1 = 0x1091 ; LOTNUM1
.equ SIGROW_SERNUM2 = 0x1092 ; LOTNUM2
.equ SIGROW_SERNUM3 = 0x1093 ; LOTNUM3
.equ SIGROW_SERNUM4 = 0x1094 ; LOTNUM4
.equ SIGROW_SERNUM5 = 0x1095 ; LOTNUM5
.equ SIGROW_SERNUM6 = 0x1096 ; RANDOM
.equ SIGROW_SERNUM7 = 0x1097 ; SCRIBE
.equ SIGROW_SERNUM8 = 0x1098 ; XPOS0
.equ SIGROW_SERNUM9 = 0x1099 ; XPOS1
.equ SIGROW_SERNUM10 = 0x109A ; YPOS0
.equ SIGROW_SERNUM11 = 0x109B ; YPOS1
.equ SIGROW_SERNUM12 = 0x109C ; RES0
.equ SIGROW_SERNUM13 = 0x109D ; RES1
.equ SIGROW_SERNUM14 = 0x109E ; RES2
.equ SIGROW_SERNUM15 = 0x109F ; RES3
;*************************************************************************
;** SLPCTRL - Sleep Controller
;*************************************************************************
.equ SLPCTRL_CTRLA = 0x0050 ; Control A
.equ SLPCTRL_VREGCTRL = 0x0051 ; Control B
;*************************************************************************
;** SPI0 - Serial Peripheral Interface
;*************************************************************************
.equ SPI0_CTRLA = 0x0940 ; Control A
.equ SPI0_CTRLB = 0x0941 ; Control B
.equ SPI0_INTCTRL = 0x0942 ; Interrupt Control
.equ SPI0_INTFLAGS = 0x0943 ; Interrupt Flags
.equ SPI0_DATA = 0x0944 ; Data
;*************************************************************************
;** SYSCFG - System Configuration Registers
;*************************************************************************
.equ SYSCFG_REVID = 0x0F01 ; Revision ID
.equ SYSCFG_VUSBCTRL = 0x0F06 ; USB Voltage System Control
;*************************************************************************
;** TCA0 - 16-bit Timer/Counter Type A
;*************************************************************************
.equ TCA0_SINGLE_CTRLA = 0x0A00 ; SINGLE Control A
.equ TCA0_SPLIT_CTRLA = 0x0A00 ; SPLIT Control A
.equ TCA0_SINGLE_CTRLB = 0x0A01 ; SINGLE Control B
.equ TCA0_SPLIT_CTRLB = 0x0A01 ; SPLIT Control B
.equ TCA0_SINGLE_CTRLC = 0x0A02 ; SINGLE Control C
.equ TCA0_SPLIT_CTRLC = 0x0A02 ; SPLIT Control C
.equ TCA0_SINGLE_CTRLD = 0x0A03 ; SINGLE Control D
.equ TCA0_SPLIT_CTRLD = 0x0A03 ; SPLIT Control D
.equ TCA0_SINGLE_CTRLECLR = 0x0A04 ; SINGLE Control E Clear
.equ TCA0_SPLIT_CTRLECLR = 0x0A04 ; SPLIT Control E Clear
.equ TCA0_SINGLE_CTRLESET = 0x0A05 ; SINGLE Control E Set
.equ TCA0_SPLIT_CTRLESET = 0x0A05 ; SPLIT Control E Set
.equ TCA0_SINGLE_CTRLFCLR = 0x0A06 ; SINGLE Control F Clear
.equ TCA0_SINGLE_CTRLFSET = 0x0A07 ; SINGLE Control F Set
.equ TCA0_SINGLE_EVCTRL = 0x0A09 ; SINGLE Event Control
.equ TCA0_SINGLE_INTCTRL = 0x0A0A ; SINGLE Interrupt Control
.equ TCA0_SPLIT_INTCTRL = 0x0A0A ; SPLIT Interrupt Control
.equ TCA0_SINGLE_INTFLAGS = 0x0A0B ; SINGLE Interrupt Flags
.equ TCA0_SPLIT_INTFLAGS = 0x0A0B ; SPLIT Interrupt Flags
.equ TCA0_SINGLE_DBGCTRL = 0x0A0E ; SINGLE Debug Control
.equ TCA0_SPLIT_DBGCTRL = 0x0A0E ; SPLIT Debug Control
.equ TCA0_SINGLE_TEMP = 0x0A0F ; SINGLE Temporary data for 16-bit Access
.equ TCA0_SINGLE_CNT = 0x0A20 ; SINGLE Count
.equ TCA0_SINGLE_CNTL = 0x0A20 ; SINGLE Count low byte
.equ TCA0_SINGLE_CNTH = 0x0A21 ; SINGLE Count hi byte
.equ TCA0_SPLIT_LCNT = 0x0A20 ; SPLIT Low Count
.equ TCA0_SPLIT_HCNT = 0x0A21 ; SPLIT High Count
.equ TCA0_SINGLE_PER = 0x0A26 ; SINGLE Period
.equ TCA0_SINGLE_PERL = 0x0A26 ; SINGLE Period low byte
.equ TCA0_SINGLE_PERH = 0x0A27 ; SINGLE Period hi byte
.equ TCA0_SPLIT_LPER = 0x0A26 ; SPLIT Low Period
.equ TCA0_SPLIT_HPER = 0x0A27 ; SPLIT High Period
.equ TCA0_SINGLE_CMP0 = 0x0A28 ; SINGLE Compare 0
.equ TCA0_SINGLE_CMP0L = 0x0A28 ; SINGLE Compare 0 low byte
.equ TCA0_SINGLE_CMP0H = 0x0A29 ; SINGLE Compare 0 hi byte
.equ TCA0_SPLIT_LCMP0 = 0x0A28 ; SPLIT Low Compare
.equ TCA0_SPLIT_HCMP0 = 0x0A29 ; SPLIT High Compare
.equ TCA0_SINGLE_CMP1 = 0x0A2A ; SINGLE Compare 1
.equ TCA0_SINGLE_CMP1L = 0x0A2A ; SINGLE Compare 1 low byte
.equ TCA0_SINGLE_CMP1H = 0x0A2B ; SINGLE Compare 1 hi byte
.equ TCA0_SPLIT_LCMP1 = 0x0A2A ; SPLIT Low Compare
.equ TCA0_SPLIT_HCMP1 = 0x0A2B ; SPLIT High Compare
.equ TCA0_SINGLE_CMP2 = 0x0A2C ; SINGLE Compare 2
.equ TCA0_SINGLE_CMP2L = 0x0A2C ; SINGLE Compare 2 low byte
.equ TCA0_SINGLE_CMP2H = 0x0A2D ; SINGLE Compare 2 hi byte
.equ TCA0_SPLIT_LCMP2 = 0x0A2C ; SPLIT Low Compare
.equ TCA0_SPLIT_HCMP2 = 0x0A2D ; SPLIT High Compare
.equ TCA0_SINGLE_PERBUF = 0x0A36 ; SINGLE Period Buffer
.equ TCA0_SINGLE_PERBUFL = 0x0A36 ; SINGLE Period Buffer low byte
.equ TCA0_SINGLE_PERBUFH = 0x0A37 ; SINGLE Period Buffer hi byte
.equ TCA0_SINGLE_CMP0BUF = 0x0A38 ; SINGLE Compare 0 Buffer
.equ TCA0_SINGLE_CMP0BUFL = 0x0A38 ; SINGLE Compare 0 Buffer low byte
.equ TCA0_SINGLE_CMP0BUFH = 0x0A39 ; SINGLE Compare 0 Buffer hi byte
.equ TCA0_SINGLE_CMP1BUF = 0x0A3A ; SINGLE Compare 1 Buffer
.equ TCA0_SINGLE_CMP1BUFL = 0x0A3A ; SINGLE Compare 1 Buffer low byte
.equ TCA0_SINGLE_CMP1BUFH = 0x0A3B ; SINGLE Compare 1 Buffer hi byte
.equ TCA0_SINGLE_CMP2BUF = 0x0A3C ; SINGLE Compare 2 Buffer
.equ TCA0_SINGLE_CMP2BUFL = 0x0A3C ; SINGLE Compare 2 Buffer low byte
.equ TCA0_SINGLE_CMP2BUFH = 0x0A3D ; SINGLE Compare 2 Buffer hi byte
;*************************************************************************
;** TCB0 - 16-bit Timer Type B
;*************************************************************************
.equ TCB0_CTRLA = 0x0B00 ; Control A
.equ TCB0_CTRLB = 0x0B01 ; Control Register B
.equ TCB0_EVCTRL = 0x0B04 ; Event Control
.equ TCB0_INTCTRL = 0x0B05 ; Interrupt Control
.equ TCB0_INTFLAGS = 0x0B06 ; Interrupt Flags
.equ TCB0_STATUS = 0x0B07 ; Status
.equ TCB0_DBGCTRL = 0x0B08 ; Debug Control
.equ TCB0_TEMP = 0x0B09 ; Temporary Value
.equ TCB0_CNT = 0x0B0A ; Count
.equ TCB0_CNTL = 0x0B0A ; Count low byte
.equ TCB0_CNTH = 0x0B0B ; Count hi byte
.equ TCB0_CCMP = 0x0B0C ; Compare or Capture
.equ TCB0_CCMPL = 0x0B0C ; Compare or Capture low byte
.equ TCB0_CCMPH = 0x0B0D ; Compare or Capture hi byte
;*************************************************************************
;** TCB1 - 16-bit Timer Type B
;*************************************************************************
.equ TCB1_CTRLA = 0x0B10 ; Control A
.equ TCB1_CTRLB = 0x0B11 ; Control Register B
.equ TCB1_EVCTRL = 0x0B14 ; Event Control
.equ TCB1_INTCTRL = 0x0B15 ; Interrupt Control
.equ TCB1_INTFLAGS = 0x0B16 ; Interrupt Flags
.equ TCB1_STATUS = 0x0B17 ; Status
.equ TCB1_DBGCTRL = 0x0B18 ; Debug Control
.equ TCB1_TEMP = 0x0B19 ; Temporary Value
.equ TCB1_CNT = 0x0B1A ; Count
.equ TCB1_CNTL = 0x0B1A ; Count low byte
.equ TCB1_CNTH = 0x0B1B ; Count hi byte
.equ TCB1_CCMP = 0x0B1C ; Compare or Capture
.equ TCB1_CCMPL = 0x0B1C ; Compare or Capture low byte
.equ TCB1_CCMPH = 0x0B1D ; Compare or Capture hi byte
;*************************************************************************
;** TWI0 - Two-Wire Interface
;*************************************************************************
.equ TWI0_CTRLA = 0x0900 ; Control A
.equ TWI0_DBGCTRL = 0x0902 ; Debug Control
.equ TWI0_MCTRLA = 0x0903 ; Host Control A
.equ TWI0_MCTRLB = 0x0904 ; Host Control B
.equ TWI0_MSTATUS = 0x0905 ; Host STATUS
.equ TWI0_MBAUD = 0x0906 ; Host Baud Rate
.equ TWI0_MADDR = 0x0907 ; Host Address
.equ TWI0_MDATA = 0x0908 ; Host Data
.equ TWI0_SCTRLA = 0x0909 ; Client Control A
.equ TWI0_SCTRLB = 0x090A ; Client Control B
.equ TWI0_SSTATUS = 0x090B ; Client Status
.equ TWI0_SADDR = 0x090C ; Client Address
.equ TWI0_SDATA = 0x090D ; Client Data
.equ TWI0_SADDRMASK = 0x090E ; Client Address Mask
;*************************************************************************
;** USART0 - Universal Synchronous and Asynchronous Receiver and Transmitter
;*************************************************************************
.equ USART0_RXDATAL = 0x0800 ; Receive Data Low Byte
.equ USART0_RXDATAH = 0x0801 ; Receive Data High Byte
.equ USART0_TXDATAL = 0x0802 ; Transmit Data Low Byte
.equ USART0_TXDATAH = 0x0803 ; Transmit Data High Byte
.equ USART0_STATUS = 0x0804 ; Status
.equ USART0_CTRLA = 0x0805 ; Control A
.equ USART0_CTRLB = 0x0806 ; Control B
.equ USART0_CTRLC = 0x0807 ; Control C
.equ USART0_BAUD = 0x0808 ; Baud Rate
.equ USART0_BAUDL = 0x0808 ; Baud Rate low byte
.equ USART0_BAUDH = 0x0809 ; Baud Rate hi byte
.equ USART0_CTRLD = 0x080A ; Control D
.equ USART0_DBGCTRL = 0x080B ; Debug Control
.equ USART0_EVCTRL = 0x080C ; Event Control
.equ USART0_TXPLCTRL = 0x080D ; IRCOM Transmitter Pulse Length Control
.equ USART0_RXPLCTRL = 0x080E ; IRCOM Receiver Pulse Length Control
;*************************************************************************
;** USART1 - Universal Synchronous and Asynchronous Receiver and Transmitter
;*************************************************************************
.equ USART1_RXDATAL = 0x0820 ; Receive Data Low Byte
.equ USART1_RXDATAH = 0x0821 ; Receive Data High Byte
.equ USART1_TXDATAL = 0x0822 ; Transmit Data Low Byte
.equ USART1_TXDATAH = 0x0823 ; Transmit Data High Byte
.equ USART1_STATUS = 0x0824 ; Status
.equ USART1_CTRLA = 0x0825 ; Control A
.equ USART1_CTRLB = 0x0826 ; Control B
.equ USART1_CTRLC = 0x0827 ; Control C
.equ USART1_BAUD = 0x0828 ; Baud Rate
.equ USART1_BAUDL = 0x0828 ; Baud Rate low byte
.equ USART1_BAUDH = 0x0829 ; Baud Rate hi byte
.equ USART1_CTRLD = 0x082A ; Control D
.equ USART1_DBGCTRL = 0x082B ; Debug Control
.equ USART1_EVCTRL = 0x082C ; Event Control
.equ USART1_TXPLCTRL = 0x082D ; IRCOM Transmitter Pulse Length Control
.equ USART1_RXPLCTRL = 0x082E ; IRCOM Receiver Pulse Length Control
;*************************************************************************
;** USB0 - USB Device Controller
;*************************************************************************
.equ USB0_CTRLA = 0x0C00 ; Control A
.equ USB0_CTRLB = 0x0C01 ; Control B
.equ USB0_BUSSTATE = 0x0C02 ; Bus State
.equ USB0_ADDR = 0x0C03 ; Address
.equ USB0_FIFOWP = 0x0C04 ; FIFO Write Pointer
.equ USB0_FIFORP = 0x0C05 ; FIFO Read Pointer
.equ USB0_EPPTR = 0x0C06 ; Endpoint Configuration Table Pointer
.equ USB0_EPPTRL = 0x0C06 ; Endpoint Configuration Table Pointer low byte
.equ USB0_EPPTRH = 0x0C07 ; Endpoint Configuration Table Pointer hi byte
.equ USB0_INTCTRLA = 0x0C08 ; Interrupt Control A
.equ USB0_INTCTRLB = 0x0C09 ; Interrupt Control B
.equ USB0_INTFLAGSA = 0x0C0A ; Interrupt Flags A
.equ USB0_INTFLAGSB = 0x0C0B ; Interrupt Flags B
.equ USB0_STATUS0_OUTCLR = 0x0C40 ; Endpoint n OUT Status Clear
.equ USB0_STATUS0_OUTSET = 0x0C41 ; Endpoint n OUT Status Set
.equ USB0_STATUS0_INCLR = 0x0C42 ; Endpoint n IN Status Clear
.equ USB0_STATUS0_INSET = 0x0C43 ; Endpoint n IN Status Set
.equ USB0_STATUS1_OUTCLR = 0x0C44 ; Endpoint n OUT Status Clear
.equ USB0_STATUS1_OUTSET = 0x0C45 ; Endpoint n OUT Status Set
.equ USB0_STATUS1_INCLR = 0x0C46 ; Endpoint n IN Status Clear
.equ USB0_STATUS1_INSET = 0x0C47 ; Endpoint n IN Status Set
.equ USB0_STATUS2_OUTCLR = 0x0C48 ; Endpoint n OUT Status Clear
.equ USB0_STATUS2_OUTSET = 0x0C49 ; Endpoint n OUT Status Set
.equ USB0_STATUS2_INCLR = 0x0C4A ; Endpoint n IN Status Clear
.equ USB0_STATUS2_INSET = 0x0C4B ; Endpoint n IN Status Set
.equ USB0_STATUS3_OUTCLR = 0x0C4C ; Endpoint n OUT Status Clear
.equ USB0_STATUS3_OUTSET = 0x0C4D ; Endpoint n OUT Status Set
.equ USB0_STATUS3_INCLR = 0x0C4E ; Endpoint n IN Status Clear
.equ USB0_STATUS3_INSET = 0x0C4F ; Endpoint n IN Status Set
.equ USB0_STATUS4_OUTCLR = 0x0C50 ; Endpoint n OUT Status Clear
.equ USB0_STATUS4_OUTSET = 0x0C51 ; Endpoint n OUT Status Set
.equ USB0_STATUS4_INCLR = 0x0C52 ; Endpoint n IN Status Clear
.equ USB0_STATUS4_INSET = 0x0C53 ; Endpoint n IN Status Set
.equ USB0_STATUS5_OUTCLR = 0x0C54 ; Endpoint n OUT Status Clear
.equ USB0_STATUS5_OUTSET = 0x0C55 ; Endpoint n OUT Status Set
.equ USB0_STATUS5_INCLR = 0x0C56 ; Endpoint n IN Status Clear
.equ USB0_STATUS5_INSET = 0x0C57 ; Endpoint n IN Status Set
.equ USB0_STATUS6_OUTCLR = 0x0C58 ; Endpoint n OUT Status Clear
.equ USB0_STATUS6_OUTSET = 0x0C59 ; Endpoint n OUT Status Set
.equ USB0_STATUS6_INCLR = 0x0C5A ; Endpoint n IN Status Clear
.equ USB0_STATUS6_INSET = 0x0C5B ; Endpoint n IN Status Set
.equ USB0_STATUS7_OUTCLR = 0x0C5C ; Endpoint n OUT Status Clear
.equ USB0_STATUS7_OUTSET = 0x0C5D ; Endpoint n OUT Status Set
.equ USB0_STATUS7_INCLR = 0x0C5E ; Endpoint n IN Status Clear
.equ USB0_STATUS7_INSET = 0x0C5F ; Endpoint n IN Status Set
.equ USB0_STATUS8_OUTCLR = 0x0C60 ; Endpoint n OUT Status Clear
.equ USB0_STATUS8_OUTSET = 0x0C61 ; Endpoint n OUT Status Set
.equ USB0_STATUS8_INCLR = 0x0C62 ; Endpoint n IN Status Clear
.equ USB0_STATUS8_INSET = 0x0C63 ; Endpoint n IN Status Set
.equ USB0_STATUS9_OUTCLR = 0x0C64 ; Endpoint n OUT Status Clear
.equ USB0_STATUS9_OUTSET = 0x0C65 ; Endpoint n OUT Status Set
.equ USB0_STATUS9_INCLR = 0x0C66 ; Endpoint n IN Status Clear
.equ USB0_STATUS9_INSET = 0x0C67 ; Endpoint n IN Status Set
.equ USB0_STATUS10_OUTCLR = 0x0C68 ; Endpoint n OUT Status Clear
.equ USB0_STATUS10_OUTSET = 0x0C69 ; Endpoint n OUT Status Set
.equ USB0_STATUS10_INCLR = 0x0C6A ; Endpoint n IN Status Clear
.equ USB0_STATUS10_INSET = 0x0C6B ; Endpoint n IN Status Set
.equ USB0_STATUS11_OUTCLR = 0x0C6C ; Endpoint n OUT Status Clear
.equ USB0_STATUS11_OUTSET = 0x0C6D ; Endpoint n OUT Status Set
.equ USB0_STATUS11_INCLR = 0x0C6E ; Endpoint n IN Status Clear
.equ USB0_STATUS11_INSET = 0x0C6F ; Endpoint n IN Status Set
.equ USB0_STATUS12_OUTCLR = 0x0C70 ; Endpoint n OUT Status Clear
.equ USB0_STATUS12_OUTSET = 0x0C71 ; Endpoint n OUT Status Set
.equ USB0_STATUS12_INCLR = 0x0C72 ; Endpoint n IN Status Clear
.equ USB0_STATUS12_INSET = 0x0C73 ; Endpoint n IN Status Set
.equ USB0_STATUS13_OUTCLR = 0x0C74 ; Endpoint n OUT Status Clear
.equ USB0_STATUS13_OUTSET = 0x0C75 ; Endpoint n OUT Status Set
.equ USB0_STATUS13_INCLR = 0x0C76 ; Endpoint n IN Status Clear
.equ USB0_STATUS13_INSET = 0x0C77 ; Endpoint n IN Status Set
.equ USB0_STATUS14_OUTCLR = 0x0C78 ; Endpoint n OUT Status Clear
.equ USB0_STATUS14_OUTSET = 0x0C79 ; Endpoint n OUT Status Set
.equ USB0_STATUS14_INCLR = 0x0C7A ; Endpoint n IN Status Clear
.equ USB0_STATUS14_INSET = 0x0C7B ; Endpoint n IN Status Set
.equ USB0_STATUS15_OUTCLR = 0x0C7C ; Endpoint n OUT Status Clear
.equ USB0_STATUS15_OUTSET = 0x0C7D ; Endpoint n OUT Status Set
.equ USB0_STATUS15_INCLR = 0x0C7E ; Endpoint n IN Status Clear
.equ USB0_STATUS15_INSET = 0x0C7F ; Endpoint n IN Status Set
;*************************************************************************
;** USERROW - User Row
;*************************************************************************
.equ USERROW_USERROW0 = 0x1200 ; User Row 0
.equ USERROW_USERROW1 = 0x1201 ; User Row 1
.equ USERROW_USERROW2 = 0x1202 ; User Row 2
.equ USERROW_USERROW3 = 0x1203 ; User Row 3
.equ USERROW_USERROW4 = 0x1204 ; User Row 4
.equ USERROW_USERROW5 = 0x1205 ; User Row 5
.equ USERROW_USERROW6 = 0x1206 ; User Row 6
.equ USERROW_USERROW7 = 0x1207 ; User Row 7
.equ USERROW_USERROW8 = 0x1208 ; User Row 8
.equ USERROW_USERROW9 = 0x1209 ; User Row 9
.equ USERROW_USERROW10 = 0x120A ; User Row 10
.equ USERROW_USERROW11 = 0x120B ; User Row 11
.equ USERROW_USERROW12 = 0x120C ; User Row 12
.equ USERROW_USERROW13 = 0x120D ; User Row 13
.equ USERROW_USERROW14 = 0x120E ; User Row 14
.equ USERROW_USERROW15 = 0x120F ; User Row 15
.equ USERROW_USERROW16 = 0x1210 ; User Row 16