StructuredBuffer<uint64_t4> In : register(t0);
RWStructuredBuffer<uint64_t> Out1 : register(u1);
RWStructuredBuffer<uint64_t2> Out2 : register(u2);
RWStructuredBuffer<uint64_t3> Out3 : register(u3);
RWStructuredBuffer<uint64_t4> Out4 : register(u4);
RWStructuredBuffer<uint64_t4> Out5 : register(u5);
[numthreads(4,1,1)]
void main(uint3 TID : SV_GroupThreadID) {
uint64_t4 V64 = In[TID.x];
Out1[TID.x] = WaveActiveBitXor(V64.x);
// 3 thread case
if (TID.x != 1)
Out1[TID.x + 4] = WaveActiveBitXor(V64.x);
Out2[TID.x] = WaveActiveBitXor(V64.xy);
uint64_t3 R64_3 = WaveActiveBitXor(V64.xyz);
Out3[TID.x].xyz = R64_3;
Out4[TID.x] = WaveActiveBitXor(V64);
// constant folding
Out5[TID.x] = WaveActiveBitXor(uint64_t4(1,2,3,4));
if (TID.x != 1)
Out5[TID.x + 4] = WaveActiveBitXor(uint64_t4(1,2,3,4));
if (TID.x % 2)
Out5[TID.x + 4 * 2] = WaveActiveBitXor(uint64_t4(1,2,3,4));
if (TID.x == 1)
Out5[TID.x + 4 * 3] = WaveActiveBitXor(uint64_t4(1,2,3,4));
}
The second to last assignment, to Out5, with the % 2 condition, behaves incorrectly.
The assignment should exclude lanes 0 and 2. Then, lanes 1 and 3 should be active, cancelling each other out, and the result should be all 0s for this assignment. However, unexpectedly, the results are:
# | Data: [ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2,
# | 3, 4, 0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 0, 0, 0, 0,
# | 1, 2, 3, 4, 0, 0, 0, 0, 1, 2, 3, 4, 0, 0, 0, 0, 1, 2,
# | 3, 4, 0, 0, 0, 0, 0, 0, 0, 0 ]
So lanes 1 and 3 each write (1, 2, 3, 4), as if unaware of the other's activity. Lane 1 is not including lane 3's activity in its wave operation.
This bug is present for 64 bit int types, on the DirectX target. It is also present on 32 bit int types on the DirectX target, AND Vulkan with the clang compiler.
Given this HLSL:
The second to last assignment, to Out5, with the % 2 condition, behaves incorrectly.
The assignment should exclude lanes 0 and 2. Then, lanes 1 and 3 should be active, cancelling each other out, and the result should be all 0s for this assignment. However, unexpectedly, the results are:
So lanes 1 and 3 each write (1, 2, 3, 4), as if unaware of the other's activity. Lane 1 is not including lane 3's activity in its wave operation.
This bug is present for 64 bit int types, on the DirectX target. It is also present on 32 bit int types on the DirectX target, AND Vulkan with the clang compiler.