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namco_c148: remove assumption that it clears all irqs when writing to any irqlevel reg
1 parent 30ac67d commit bfed12c

4 files changed

Lines changed: 49 additions & 76 deletions

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‎src/mame/namco/namco_c148.cpp‎

Lines changed: 36 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,6 @@ void namco_c148_device::map(address_map &map)
9999
}
100100

101101

102-
103102
//-------------------------------------------------
104103
// device_validity_check - device-specific checks
105104
//-------------------------------------------------
@@ -137,49 +136,48 @@ void namco_c148_device::device_start()
137136

138137
void namco_c148_device::device_reset()
139138
{
140-
m_irqlevel.vblank = 0;
141-
m_irqlevel.pos = 0;
142-
m_irqlevel.sci = 0;
143-
m_irqlevel.ex = 0;
144-
m_irqlevel.cpu = 0;
139+
vblank_irq_level_w(0);
140+
pos_irq_level_w(0);
141+
cpu_irq_level_w(0);
142+
ex_irq_level_w(0);
143+
sci_irq_level_w(0);
145144
}
146145

146+
147147
//**************************************************************************
148148
// IRQ section
149149
//**************************************************************************
150150

151-
uint8_t namco_c148_device::pos_irq_level_r() { return m_irqlevel.pos & 7; }
152-
uint8_t namco_c148_device::vblank_irq_level_r() { return m_irqlevel.vblank & 7; }
153-
uint8_t namco_c148_device::cpu_irq_level_r() { return m_irqlevel.cpu & 7; }
154-
uint8_t namco_c148_device::ex_irq_level_r() { return m_irqlevel.ex & 7; }
155-
uint8_t namco_c148_device::sci_irq_level_r() { return m_irqlevel.sci & 7; }
156-
157-
inline void namco_c148_device::flush_irq_acks()
158-
{
159-
// If writing an IRQ priority register, clear any pending IRQs.
160-
// Dirt Fox and Winning Run require this behaviour
161-
// TODO: literal behaviour, Winning Run GPU doesn't seem to care about irq ack ports at all?
162-
for (int i = 0; i < 8; i++)
163-
m_hostcpu->set_input_line(i, CLEAR_LINE);
164-
}
165-
166-
void namco_c148_device::pos_irq_level_w(uint8_t data) { m_irqlevel.pos = data & 7; flush_irq_acks(); if(data != 0) { LOG("%s: pos IRQ level = %02x\n", tag(), data); } }
167-
void namco_c148_device::vblank_irq_level_w(uint8_t data) { m_irqlevel.vblank = data & 7; flush_irq_acks(); LOG("%s: vblank IRQ level = %02x\n", tag(), data); }
168-
void namco_c148_device::cpu_irq_level_w(uint8_t data) { m_irqlevel.cpu = data & 7; flush_irq_acks(); LOG("%s: cpu IRQ level = %02x\n", tag(), data); }
169-
void namco_c148_device::ex_irq_level_w(uint8_t data) { m_irqlevel.ex = data & 7; flush_irq_acks(); LOG("%s: ex IRQ level = %02x\n", tag(), data); }
170-
void namco_c148_device::sci_irq_level_w(uint8_t data) { m_irqlevel.sci = data & 7; flush_irq_acks(); LOG("%s: sci IRQ level = %02x\n", tag(), data); }
151+
uint8_t namco_c148_device::pos_irq_level_r() { return m_irqlevel.pos & 7; }
152+
uint8_t namco_c148_device::vblank_irq_level_r() { return m_irqlevel.vblank & 7; }
153+
uint8_t namco_c148_device::cpu_irq_level_r() { return m_irqlevel.cpu & 7; }
154+
uint8_t namco_c148_device::ex_irq_level_r() { return m_irqlevel.ex & 7; }
155+
uint8_t namco_c148_device::sci_irq_level_r() { return m_irqlevel.sci & 7; }
156+
157+
void namco_c148_device::vblank_irq_level_w(uint8_t data) { vblank_irq_ack_w(); m_irqlevel.vblank = data & 7; LOG("%s: vblank IRQ level = %02x\n", tag(), data); }
158+
void namco_c148_device::pos_irq_level_w(uint8_t data) { pos_irq_ack_w(); m_irqlevel.pos = data & 7; if(data != 0) { LOG("%s: pos IRQ level = %02x\n", tag(), data); } }
159+
void namco_c148_device::cpu_irq_level_w(uint8_t data) { cpu_irq_ack_w(); m_irqlevel.cpu = data & 7; LOG("%s: cpu IRQ level = %02x\n", tag(), data); }
160+
void namco_c148_device::ex_irq_level_w(uint8_t data) { ex_irq_ack_w(); m_irqlevel.ex = data & 7; LOG("%s: ex IRQ level = %02x\n", tag(), data); }
161+
void namco_c148_device::sci_irq_level_w(uint8_t data) { sci_irq_ack_w(); m_irqlevel.sci = data & 7; LOG("%s: sci IRQ level = %02x\n", tag(), data); }
162+
163+
uint16_t namco_c148_device::vblank_irq_ack_r() { if (!machine().side_effects_disabled()) m_hostcpu->set_input_line(m_irqlevel.vblank, CLEAR_LINE); return 0; }
164+
uint16_t namco_c148_device::pos_irq_ack_r() { if (!machine().side_effects_disabled()) m_hostcpu->set_input_line(m_irqlevel.pos, CLEAR_LINE); return 0; }
165+
uint16_t namco_c148_device::cpu_irq_ack_r() { if (!machine().side_effects_disabled()) m_hostcpu->set_input_line(m_irqlevel.cpu, CLEAR_LINE); return 0; }
166+
uint16_t namco_c148_device::ex_irq_ack_r() { if (!machine().side_effects_disabled()) m_hostcpu->set_input_line(m_irqlevel.ex, CLEAR_LINE); return 0; }
167+
uint16_t namco_c148_device::sci_irq_ack_r() { if (!machine().side_effects_disabled()) m_hostcpu->set_input_line(m_irqlevel.sci, CLEAR_LINE); return 0; }
168+
169+
void namco_c148_device::vblank_irq_ack_w(uint16_t data) { m_hostcpu->set_input_line(m_irqlevel.vblank, CLEAR_LINE); }
170+
void namco_c148_device::pos_irq_ack_w(uint16_t data) { m_hostcpu->set_input_line(m_irqlevel.pos, CLEAR_LINE); }
171+
void namco_c148_device::cpu_irq_ack_w(uint16_t data) { m_hostcpu->set_input_line(m_irqlevel.cpu, CLEAR_LINE); }
172+
void namco_c148_device::ex_irq_ack_w(uint16_t data) { m_hostcpu->set_input_line(m_irqlevel.ex, CLEAR_LINE); }
173+
void namco_c148_device::sci_irq_ack_w(uint16_t data) { m_hostcpu->set_input_line(m_irqlevel.sci, CLEAR_LINE); }
174+
175+
void namco_c148_device::vblank_irq_trigger() { m_hostcpu->set_input_line(m_irqlevel.vblank, HOLD_LINE); } // TODO: Phelios doesn't ack the vblank irq at all!
176+
void namco_c148_device::pos_irq_trigger() { m_hostcpu->set_input_line(m_irqlevel.pos, ASSERT_LINE); }
177+
void namco_c148_device::cpu_irq_trigger() { m_hostcpu->set_input_line(m_irqlevel.cpu, ASSERT_LINE); }
178+
void namco_c148_device::ex_irq_trigger() { m_hostcpu->set_input_line(m_irqlevel.ex, ASSERT_LINE); }
179+
void namco_c148_device::sci_irq_trigger() { m_hostcpu->set_input_line(m_irqlevel.sci, ASSERT_LINE); }
171180

172-
uint16_t namco_c148_device::vblank_irq_ack_r() { m_hostcpu->set_input_line(m_irqlevel.vblank, CLEAR_LINE); return 0; }
173-
uint16_t namco_c148_device::pos_irq_ack_r() { m_hostcpu->set_input_line(m_irqlevel.pos, CLEAR_LINE); return 0; }
174-
uint16_t namco_c148_device::cpu_irq_ack_r() { m_hostcpu->set_input_line(m_irqlevel.cpu, CLEAR_LINE); return 0; }
175-
uint16_t namco_c148_device::ex_irq_ack_r() { m_hostcpu->set_input_line(m_irqlevel.ex, CLEAR_LINE); return 0; }
176-
uint16_t namco_c148_device::sci_irq_ack_r() { m_hostcpu->set_input_line(m_irqlevel.sci, CLEAR_LINE); return 0; }
177-
178-
void namco_c148_device::vblank_irq_ack_w(uint16_t data) { m_hostcpu->set_input_line(m_irqlevel.vblank, CLEAR_LINE); }
179-
void namco_c148_device::pos_irq_ack_w(uint16_t data) { m_hostcpu->set_input_line(m_irqlevel.pos, CLEAR_LINE); }
180-
void namco_c148_device::cpu_irq_ack_w(uint16_t data) { m_hostcpu->set_input_line(m_irqlevel.cpu, CLEAR_LINE); }
181-
void namco_c148_device::ex_irq_ack_w(uint16_t data) { m_hostcpu->set_input_line(m_irqlevel.ex, CLEAR_LINE); }
182-
void namco_c148_device::sci_irq_ack_w(uint16_t data) { m_hostcpu->set_input_line(m_irqlevel.sci, CLEAR_LINE); }
183181

184182
//**************************************************************************
185183
// Comm ports
@@ -219,36 +217,11 @@ void namco_c148_device::cpu_irq_assert_w(uint16_t data)
219217
m_linked_c148->cpu_irq_trigger();
220218
}
221219

220+
222221
//**************************************************************************
223222
// GETTERS/SETTERS
224223
//**************************************************************************
225224

226-
void namco_c148_device::vblank_irq_trigger()
227-
{
228-
// TODO: Phelios doesn't ack the vblank irq at all!
229-
m_hostcpu->set_input_line(m_irqlevel.vblank, HOLD_LINE);
230-
}
231-
232-
void namco_c148_device::pos_irq_trigger()
233-
{
234-
m_hostcpu->set_input_line(m_irqlevel.pos, ASSERT_LINE);
235-
}
236-
237-
void namco_c148_device::cpu_irq_trigger()
238-
{
239-
m_hostcpu->set_input_line(m_irqlevel.cpu, ASSERT_LINE);
240-
}
241-
242-
void namco_c148_device::ex_irq_trigger()
243-
{
244-
m_hostcpu->set_input_line(m_irqlevel.ex, ASSERT_LINE);
245-
}
246-
247-
void namco_c148_device::sci_irq_trigger()
248-
{
249-
m_hostcpu->set_input_line(m_irqlevel.sci, ASSERT_LINE);
250-
}
251-
252225
// TODO: these doesn't belong here, needs C116 device
253226
uint8_t namco_c148_device::ext_posirq_line_r()
254227
{

‎src/mame/namco/namco_c148.h‎

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -45,27 +45,27 @@ class namco_c148_device : public device_t
4545
uint8_t vblank_irq_level_r();
4646
void vblank_irq_level_w(uint8_t data);
4747
uint16_t vblank_irq_ack_r();
48-
void vblank_irq_ack_w(uint16_t data);
48+
void vblank_irq_ack_w(uint16_t data = 0);
4949

5050
uint8_t pos_irq_level_r();
5151
void pos_irq_level_w(uint8_t data);
5252
uint16_t pos_irq_ack_r();
53-
void pos_irq_ack_w(uint16_t data);
53+
void pos_irq_ack_w(uint16_t data = 0);
5454

5555
uint8_t cpu_irq_level_r();
5656
void cpu_irq_level_w(uint8_t data);
5757
uint16_t cpu_irq_ack_r();
58-
void cpu_irq_ack_w(uint16_t data);
58+
void cpu_irq_ack_w(uint16_t data = 0);
5959

6060
uint8_t ex_irq_level_r();
6161
void ex_irq_level_w(uint8_t data);
6262
uint16_t ex_irq_ack_r();
63-
void ex_irq_ack_w(uint16_t data);
63+
void ex_irq_ack_w(uint16_t data = 0);
6464

6565
uint8_t sci_irq_level_r();
6666
void sci_irq_level_w(uint8_t data);
6767
uint16_t sci_irq_ack_r();
68-
void sci_irq_ack_w(uint16_t data);
68+
void sci_irq_ack_w(uint16_t data = 0);
6969

7070
uint8_t ext_posirq_line_r();
7171
void ext_posirq_line_w(uint8_t data);
@@ -98,17 +98,16 @@ class namco_c148_device : public device_t
9898
bool m_hostcpu_master; // define if host cpu is master
9999

100100
struct{
101-
uint8_t cpu;
102-
uint8_t ex;
103-
uint8_t sci;
104-
uint8_t pos;
105-
uint8_t vblank;
101+
uint8_t cpu = 0;
102+
uint8_t ex = 0;
103+
uint8_t sci = 0;
104+
uint8_t pos = 0;
105+
uint8_t vblank = 0;
106106
} m_irqlevel;
107107

108108
uint8_t m_posirq_line;
109109
uint8_t m_bus_reg;
110110

111-
void flush_irq_acks();
112111
void cpu_irq_trigger();
113112
};
114113

‎src/mame/namco/namcos2.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1496,8 +1496,8 @@ INPUT_PORTS_END
14961496

14971497
static INPUT_PORTS_START( dirtfox )
14981498
PORT_START("MCUB") /* 63B05Z0 - PORT B */
1499-
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Gear Shift Down")
1500-
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Gear Shift Up")
1499+
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME("Gear Shift Down")
1500+
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_NAME("Gear Shift Up")
15011501

15021502
NAMCOS2_MCU_PORT_C_DEFAULT
15031503

‎src/mame/namco/namcos21.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@ shade pixels according to their depth.
3737
TODO:
3838
- polygon glitches/flicker
3939
- car engine sound is wrong
40+
- pressing service mode while the game is running causes it to lock up (need to press F3)
4041
- is there a video_enable flag? or at least one for the bitmap layer (see screen transitions)
4142
- winrungp: some missing bitmap layer gfx due to underdumps of program roms (see attract mode when
4243
it's supposed to show "TRIANGLE" curve text, and the congratulations screen after winning)

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