@@ -170,7 +170,27 @@ CxPlatDpRawAssignQueue(
170170_IRQL_requires_max_ (DISPATCH_LEVEL )
171171const CXPLAT_INTERFACE *
172172CxPlatDpRawGetInterfaceFromQueue (
173- _In_ const void * Queue
173+ _In_ const CXPLAT_QUEUE * Queue
174+ );
175+
176+ //
177+ // Returns whether the L3 (i.e., network) layer transmit checksum offload is
178+ // enabled on the queue.
179+ //
180+ _IRQL_requires_max_ (DISPATCH_LEVEL )
181+ BOOLEAN
182+ CxPlatDpRawIsL3TxXsumOffloadedOnQueue (
183+ _In_ const CXPLAT_QUEUE * Queue
184+ );
185+
186+ //
187+ // Returns whether the L3 (i.e., transport) layer transmit checksum offload is
188+ // enabled on the queue.
189+ //
190+ _IRQL_requires_max_ (DISPATCH_LEVEL )
191+ BOOLEAN
192+ CxPlatDpRawIsL4TxXsumOffloadedOnQueue (
193+ _In_ const CXPLAT_QUEUE * Queue
174194 );
175195
176196typedef struct HEADER_BACKFILL {
@@ -250,6 +270,27 @@ CxPlatDpRawTxEnqueue(
250270 _In_ CXPLAT_SEND_DATA * SendData
251271 );
252272
273+ //
274+ // Sets the TX send object to have the specified L3 checksum offload settings.
275+ //
276+ _IRQL_requires_max_ (DISPATCH_LEVEL )
277+ void
278+ CxPlatDpRawTxSetL3ChecksumOffload (
279+ _In_ CXPLAT_SEND_DATA * SendData
280+ );
281+
282+ //
283+ // Sets the TX send object to have the specified L4 checksum offload settings.
284+ //
285+ _IRQL_requires_max_ (DISPATCH_LEVEL )
286+ void
287+ CxPlatDpRawTxSetL4ChecksumOffload (
288+ _In_ CXPLAT_SEND_DATA * SendData ,
289+ _In_ BOOLEAN IsIpv6 ,
290+ _In_ BOOLEAN IsTcp ,
291+ _In_ uint8_t L4HeaderLength
292+ );
293+
253294//
254295// Raw Socket Interface
255296//
372413CxPlatFramingWriteHeaders (
373414 _In_ CXPLAT_SOCKET_RAW * Socket ,
374415 _In_ const CXPLAT_ROUTE * Route ,
416+ _Inout_ CXPLAT_SEND_DATA * SendData ,
375417 _Inout_ QUIC_BUFFER * Buffer ,
376418 _In_ CXPLAT_ECN_TYPE ECN ,
377419 _In_ uint8_t DSCP ,
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