a2pico2.pio

///////////////////////////////////////////////////////////////////////////////

/*

MIT License

Copyright (c) 2026 Oliver Schmidt (https://a2retro.de/)

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

*/

///////////////////////////////////////////////////////////////////////////////

.define public  GPIO_PHI0        1
.define public  GPIO_ADDR        2  // 12 pins
.define public  GPIO_DATA       14  //  8 pins
.define public  GPIO_RW         22

.define public  SIZE_ADDR       21  // incl. DATA + R/W
.define public  SIZE_DATA        8

.define         IRQ_SYNC         0
.define         IRQ_WRITE        1

// A2Pico2Lite W //////////////////////////////////////////////////////////////

.define public  GPIO_ENBL       26
.define public  GPIO_RESET      27

// A2Pico2Lite ////////////////////////////////////////////////////////////////

.define public  GPIO_DEVSEL     26
.define public  GPIO_IOSEL      27
.define public  GPIO_IOSTRB     28

.define public  SIZE_ENBL        3  // DEVSEL + IOSEL + IOSTRB

.define         IRQ_ADDR         2

/*

Implementation of the Apple II peripheral bus protocol:

- The falling edge of /DEVSEL, /IOSEL or /IOSTRB activate the 'addr' state
  machine.

- On activation of the 'addr' state machine, the lines A0-A11, D0-D7 and R/W
  are latched and pushed into the 'addr' state machine RX FIFO.

- In case of an Apple II write cycle, the lines D0-D7 are latched ~300ns later
  and pushed into the 'write' state machine RX FIFO.

- If a byte is pushed into the 'read' state machine TX FIFO, it is driven out
  to the lines D0-D7 until /DEVSEL, /IOSEL and /IOSTRB are all high.

*/

///////////////////////////////////////////////////////////////////////////////

.program addr

.wrap_target

idle:
    wait 1 gpio GPIO_ENBL       // wait for ENBL to rise

    wait 0 gpio GPIO_ENBL       // wait for ENBL to fall

    in pins, SIZE_ADDR          // shift A0-A15 + D0-D7 + R/W into ISR

    jmp pin idle                // jump to 'idle' if R/W is high

    irq IRQ_WRITE               // set 'write' IRQ

.wrap


.program addr_indirect

.wrap_target

idle:
    wait 1 irq IRQ_ADDR         // wait for 'addr' IRQ to be set and clear it

    in pins, SIZE_ADDR          // shift A0-A15 + D0-D7 + R/W into ISR

    jmp pin idle                // jump to 'idle' if R/W is high

    irq IRQ_WRITE               // set 'write' IRQ

.wrap

% c-sdk {
static inline void addr_program_set_config(pio_sm_config *c) {

    // in_base:         GPIO_ADDR
    sm_config_set_in_pins(c, GPIO_ADDR);

    // shift_right:     false
    // autopush:        true
    // push_threshold:  SIZE_ADDR
    sm_config_set_in_shift(c, false, true, SIZE_ADDR);

    // pin:             GPIO_RW
    sm_config_set_jmp_pin(c, GPIO_RW);
}
%}

///////////////////////////////////////////////////////////////////////////////

.program write

.wrap_target

    wait 1 irq IRQ_WRITE [31]   // wait for 'write' IRQ to be set and clear it
    nop [31]                    // [31+32 cycles to allow 6502 to set up D0-D7]

    in pins, SIZE_DATA          // shift D0-D7 into ISR

.wrap

% c-sdk {
static inline void write_program_set_config(pio_sm_config *c) {

    // in_base:         GPIO_DATA
    sm_config_set_in_pins(c, GPIO_DATA);

    // shift_right:     false
    // autopush:        true
    // push_threshold:  SIZE_DATA
    sm_config_set_in_shift(c, false, true, SIZE_DATA);
}
%}

///////////////////////////////////////////////////////////////////////////////

.program read

.wrap_target

    pull block                  // pull data into OSR, block on empty FIFO

    out pins, SIZE_DATA         // shift OSR out to D0-D7

    mov pindirs, ~null          // enable output of D0-D7

    wait 1 gpio GPIO_ENBL       // wait for ENBL to rise

    mov pindirs, null           // disable output of D0-D7

.wrap


.program read_indirect

    set y, 0b111                // inactive state of DEVSEL, IOSEL and IOSTRB

.wrap_target

    pull block                  // pull data into OSR, block on empty FIFO

    out pins, SIZE_DATA         // shift OSR out to D0-D7

    mov pindirs, ~null          // enable output of D0-D7

check:
    mov x, pins                 // get DEVSEL, IOSEL and IOSTRB state

    jmp x!=y check              // jump to 'check' if not inactive state

    mov pindirs, null           // disable output of D0-D7

.wrap

% c-sdk {
static inline void read_program_set_config(pio_sm_config *c) {

    // in_base:         GPIO_DEVSEL
    sm_config_set_in_pins(c, GPIO_DEVSEL);

    // in_count:        SIZE_ENBL
    sm_config_set_in_pin_count(c, SIZE_ENBL);

    // out_base:        GPIO_DATA
    // out_count:       SIZE_DATA
    sm_config_set_out_pins(c, GPIO_DATA, SIZE_DATA);

    // shift_right:     true
    // autopull:        false
    // pull_threshold:  SIZE_DATA
    sm_config_set_out_shift(c, true, false, SIZE_DATA);
}
%}

///////////////////////////////////////////////////////////////////////////////

.program sync

    pull block                  // pull data into OSR, block on empty FIFO

.wrap_target

    mov x, osr                  // move OSR to X

loop:
    wait 1 gpio GPIO_PHI0 [31]  // wait for PHI0 to rise
    nop [31]                    // [31+32 cycles to avoid false transitions]

    wait 0 gpio GPIO_PHI0 [31]  // wait for PHI0 to fall
    nop [31]                    // [31+32 cycles to avoid false transitions]

    jmp x-- loop                // jump to 'loop' if X != 0, prior to decrement

    irq IRQ_SYNC                // set 'sync' IRQ

.wrap

///////////////////////////////////////////////////////////////////////////////

.program devsel

.wrap_target

    wait 0 gpio GPIO_DEVSEL     // wait for DEVSEL to fall

    irq prev set IRQ_ADDR       // set 'addr' IRQ on previous PIO block

    wait 1 gpio GPIO_DEVSEL     // wait for DEVSEL to rise

.wrap

///////////////////////////////////////////////////////////////////////////////

.program iosel

.wrap_target

    wait 0 gpio GPIO_IOSEL      // wait for IOSEL to fall

    irq prev set IRQ_ADDR       // set 'addr' IRQ on previous PIO block

    wait 1 gpio GPIO_IOSEL      // wait for IOSEL to rise

.wrap

///////////////////////////////////////////////////////////////////////////////

.program iostrb

.wrap_target

    wait 0 gpio GPIO_IOSTRB     // wait for IOSTRB to fall

    irq prev set IRQ_ADDR       // set 'addr' IRQ on previous PIO block

    wait 1 gpio GPIO_IOSTRB     // wait for IOSTRB to rise

.wrap

///////////////////////////////////////////////////////////////////////////////