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feat(RISCVCombines): simplify zextw zextb chains
1 parent 890c3f0 commit 897c18b

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Lines changed: 324 additions & 21 deletions

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‎Test/Passes/RISCVCombines/zextw_slliw_zextb.mlir‎

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// RUN: veir-opt %s -p=riscv-combine | filecheck %s
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"builtin.module"() ({
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"func.func"() <{function_type = (!riscv.reg) -> !riscv.reg, sym_name = "byte_shift"}> ({
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^bb0(%x : !riscv.reg):
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%zextb = "riscv.zextb"(%x) : (!riscv.reg) -> !riscv.reg
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%zextw = "riscv.zextw"(%zextb) : (!riscv.reg) -> !riscv.reg
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%slliw = "riscv.slliw"(%zextw) <{"value" = 24 : i64}> : (!riscv.reg) -> !riscv.reg
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%out = "riscv.zextw"(%slliw) : (!riscv.reg) -> !riscv.reg
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"func.return"(%out) : (!riscv.reg) -> ()
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}) : () -> ()
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"func.func"() <{function_type = (!riscv.reg) -> !riscv.reg, sym_name = "shift_too_large"}> ({
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^bb0(%x : !riscv.reg):
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%zextb = "riscv.zextb"(%x) : (!riscv.reg) -> !riscv.reg
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%slliw = "riscv.slliw"(%zextb) <{"value" = 25 : i64}> : (!riscv.reg) -> !riscv.reg
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%out = "riscv.zextw"(%slliw) : (!riscv.reg) -> !riscv.reg
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"func.return"(%out) : (!riscv.reg) -> ()
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}) : () -> ()
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// Cover every statically instantiated Puddle pattern for the valid shift range.
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"func.func"() <{function_type = (!riscv.reg) -> (!riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg), sym_name = "all_byte_shifts"}> ({
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^bb0(%x : !riscv.reg):
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%zextb = "riscv.zextb"(%x) : (!riscv.reg) -> !riscv.reg
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%slliw0 = "riscv.slliw"(%zextb) <{"value" = 0 : i64}> : (!riscv.reg) -> !riscv.reg
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%out0 = "riscv.zextw"(%slliw0) : (!riscv.reg) -> !riscv.reg
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%slliw1 = "riscv.slliw"(%zextb) <{"value" = 1 : i64}> : (!riscv.reg) -> !riscv.reg
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%out1 = "riscv.zextw"(%slliw1) : (!riscv.reg) -> !riscv.reg
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%slliw2 = "riscv.slliw"(%zextb) <{"value" = 2 : i64}> : (!riscv.reg) -> !riscv.reg
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%out2 = "riscv.zextw"(%slliw2) : (!riscv.reg) -> !riscv.reg
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%slliw3 = "riscv.slliw"(%zextb) <{"value" = 3 : i64}> : (!riscv.reg) -> !riscv.reg
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%out3 = "riscv.zextw"(%slliw3) : (!riscv.reg) -> !riscv.reg
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%slliw4 = "riscv.slliw"(%zextb) <{"value" = 4 : i64}> : (!riscv.reg) -> !riscv.reg
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%out4 = "riscv.zextw"(%slliw4) : (!riscv.reg) -> !riscv.reg
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%slliw5 = "riscv.slliw"(%zextb) <{"value" = 5 : i64}> : (!riscv.reg) -> !riscv.reg
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%out5 = "riscv.zextw"(%slliw5) : (!riscv.reg) -> !riscv.reg
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%slliw6 = "riscv.slliw"(%zextb) <{"value" = 6 : i64}> : (!riscv.reg) -> !riscv.reg
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%out6 = "riscv.zextw"(%slliw6) : (!riscv.reg) -> !riscv.reg
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%slliw7 = "riscv.slliw"(%zextb) <{"value" = 7 : i64}> : (!riscv.reg) -> !riscv.reg
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%out7 = "riscv.zextw"(%slliw7) : (!riscv.reg) -> !riscv.reg
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%slliw8 = "riscv.slliw"(%zextb) <{"value" = 8 : i64}> : (!riscv.reg) -> !riscv.reg
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%out8 = "riscv.zextw"(%slliw8) : (!riscv.reg) -> !riscv.reg
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%slliw9 = "riscv.slliw"(%zextb) <{"value" = 9 : i64}> : (!riscv.reg) -> !riscv.reg
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%out9 = "riscv.zextw"(%slliw9) : (!riscv.reg) -> !riscv.reg
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%slliw10 = "riscv.slliw"(%zextb) <{"value" = 10 : i64}> : (!riscv.reg) -> !riscv.reg
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%out10 = "riscv.zextw"(%slliw10) : (!riscv.reg) -> !riscv.reg
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%slliw11 = "riscv.slliw"(%zextb) <{"value" = 11 : i64}> : (!riscv.reg) -> !riscv.reg
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%out11 = "riscv.zextw"(%slliw11) : (!riscv.reg) -> !riscv.reg
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%slliw12 = "riscv.slliw"(%zextb) <{"value" = 12 : i64}> : (!riscv.reg) -> !riscv.reg
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%out12 = "riscv.zextw"(%slliw12) : (!riscv.reg) -> !riscv.reg
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%slliw13 = "riscv.slliw"(%zextb) <{"value" = 13 : i64}> : (!riscv.reg) -> !riscv.reg
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%out13 = "riscv.zextw"(%slliw13) : (!riscv.reg) -> !riscv.reg
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%slliw14 = "riscv.slliw"(%zextb) <{"value" = 14 : i64}> : (!riscv.reg) -> !riscv.reg
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%out14 = "riscv.zextw"(%slliw14) : (!riscv.reg) -> !riscv.reg
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%slliw15 = "riscv.slliw"(%zextb) <{"value" = 15 : i64}> : (!riscv.reg) -> !riscv.reg
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%out15 = "riscv.zextw"(%slliw15) : (!riscv.reg) -> !riscv.reg
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%slliw16 = "riscv.slliw"(%zextb) <{"value" = 16 : i64}> : (!riscv.reg) -> !riscv.reg
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%out16 = "riscv.zextw"(%slliw16) : (!riscv.reg) -> !riscv.reg
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%slliw17 = "riscv.slliw"(%zextb) <{"value" = 17 : i64}> : (!riscv.reg) -> !riscv.reg
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%out17 = "riscv.zextw"(%slliw17) : (!riscv.reg) -> !riscv.reg
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%slliw18 = "riscv.slliw"(%zextb) <{"value" = 18 : i64}> : (!riscv.reg) -> !riscv.reg
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%out18 = "riscv.zextw"(%slliw18) : (!riscv.reg) -> !riscv.reg
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%slliw19 = "riscv.slliw"(%zextb) <{"value" = 19 : i64}> : (!riscv.reg) -> !riscv.reg
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%out19 = "riscv.zextw"(%slliw19) : (!riscv.reg) -> !riscv.reg
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%slliw20 = "riscv.slliw"(%zextb) <{"value" = 20 : i64}> : (!riscv.reg) -> !riscv.reg
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%out20 = "riscv.zextw"(%slliw20) : (!riscv.reg) -> !riscv.reg
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%slliw21 = "riscv.slliw"(%zextb) <{"value" = 21 : i64}> : (!riscv.reg) -> !riscv.reg
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%out21 = "riscv.zextw"(%slliw21) : (!riscv.reg) -> !riscv.reg
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%slliw22 = "riscv.slliw"(%zextb) <{"value" = 22 : i64}> : (!riscv.reg) -> !riscv.reg
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%out22 = "riscv.zextw"(%slliw22) : (!riscv.reg) -> !riscv.reg
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%slliw23 = "riscv.slliw"(%zextb) <{"value" = 23 : i64}> : (!riscv.reg) -> !riscv.reg
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%out23 = "riscv.zextw"(%slliw23) : (!riscv.reg) -> !riscv.reg
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%slliw24 = "riscv.slliw"(%zextb) <{"value" = 24 : i64}> : (!riscv.reg) -> !riscv.reg
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%out24 = "riscv.zextw"(%slliw24) : (!riscv.reg) -> !riscv.reg
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"func.return"(%out0, %out1, %out2, %out3, %out4, %out5, %out6, %out7, %out8, %out9, %out10, %out11, %out12, %out13, %out14, %out15, %out16, %out17, %out18, %out19, %out20, %out21, %out22, %out23, %out24) : (!riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg) -> ()
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}) : () -> ()
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// The newly created `slli` must take the root's `x4` result type, not become
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// an unallocated `!riscv.reg` value.
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"func.func"() <{function_type = (!riscv.reg<x1>) -> !riscv.reg<x4>, sym_name = "typed_byte_shift"}> ({
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^bb0(%x : !riscv.reg<x1>):
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%zextb = "riscv.zextb"(%x) : (!riscv.reg<x1>) -> !riscv.reg<x2>
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%slliw = "riscv.slliw"(%zextb) <{"value" = 24 : i64}> : (!riscv.reg<x2>) -> !riscv.reg<x3>
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%out = "riscv.zextw"(%slliw) : (!riscv.reg<x3>) -> !riscv.reg<x4>
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"func.return"(%out) : (!riscv.reg<x4>) -> ()
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}) : () -> ()
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}) : () -> ()
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// CHECK-LABEL: "sym_name" = "byte_shift"
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// CHECK: ^{{.*}}(%[[SHIFT_X:.*]] : !riscv.reg):
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// CHECK-NEXT: %[[SHIFT_B:.*]] = "riscv.zextb"(%[[SHIFT_X]]) : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %[[SHIFT:.*]] = "riscv.slli"(%[[SHIFT_B]]) <{"value" = 24 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: "func.return"(%[[SHIFT]]) : (!riscv.reg) -> ()
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// CHECK-LABEL: "sym_name" = "shift_too_large"
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// CHECK: ^{{.*}}(%[[LARGE_X:.*]] : !riscv.reg):
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// CHECK-NEXT: %[[LARGE_B:.*]] = "riscv.zextb"(%[[LARGE_X]]) : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %[[LARGE_SHIFT:.*]] = "riscv.slliw"(%[[LARGE_B]]) <{"value" = 25 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %[[LARGE_OUT:.*]] = "riscv.zextw"(%[[LARGE_SHIFT]]) : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: "func.return"(%[[LARGE_OUT]]) : (!riscv.reg) -> ()
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// CHECK-LABEL: "sym_name" = "all_byte_shifts"
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// CHECK: ^{{.*}}(%[[ALL_X:.*]] : !riscv.reg):
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// CHECK-NEXT: %[[ALL_B:.*]] = "riscv.zextb"(%[[ALL_X]]) : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 0 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 1 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 2 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 3 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 4 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 5 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 6 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 7 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 8 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 9 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 10 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 11 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 12 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 13 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 14 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 15 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 16 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 17 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 18 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 19 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 20 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 21 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 22 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 23 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: %{{.*}} = "riscv.slli"(%[[ALL_B]]) <{"value" = 24 : i64}> : (!riscv.reg) -> !riscv.reg
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// CHECK-LABEL: "sym_name" = "typed_byte_shift"
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// CHECK: ^{{.*}}(%[[TYPED_SHIFT_X:.*]] : !riscv.reg<x1>):
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// CHECK-NEXT: %[[TYPED_SHIFT_B:.*]] = "riscv.zextb"(%[[TYPED_SHIFT_X]]) : (!riscv.reg<x1>) -> !riscv.reg<x2>
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// CHECK-NEXT: %[[TYPED_SHIFT:.*]] = "riscv.slli"(%[[TYPED_SHIFT_B]]) <{"value" = 24 : i64}> : (!riscv.reg<x2>) -> !riscv.reg<x4>
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// CHECK-NEXT: "func.return"(%[[TYPED_SHIFT]]) : (!riscv.reg<x4>) -> ()

‎Test/Passes/RISCVCombines/zextw_zextb.mlir‎

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// RUN: veir-opt %s -p=riscv-combine | filecheck %s
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"builtin.module"() ({
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"func.func"() <{function_type = (!riscv.reg) -> !riscv.reg, sym_name = "nested_zext"}> ({
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^bb0(%x : !riscv.reg):
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%zextb = "riscv.zextb"(%x) : (!riscv.reg) -> !riscv.reg
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%zextw = "riscv.zextw"(%zextb) : (!riscv.reg) -> !riscv.reg
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"func.return"(%zextw) : (!riscv.reg) -> ()
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}) : () -> ()
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// The inner result and root use the same fixed register.
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"func.func"() <{function_type = (!riscv.reg<x1>) -> !riscv.reg<x3>, sym_name = "typed_nested_zext"}> ({
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^bb0(%x : !riscv.reg<x1>):
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%zextb = "riscv.zextb"(%x) : (!riscv.reg<x1>) -> !riscv.reg<x3>
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%zextw = "riscv.zextw"(%zextb) : (!riscv.reg<x3>) -> !riscv.reg<x3>
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"func.return"(%zextw) : (!riscv.reg<x3>) -> ()
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}) : () -> ()
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// Matching register types use forwarding even when the inner op is shared.
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"func.func"() <{function_type = (!riscv.reg<x1>) -> (!riscv.reg<x3>, !riscv.reg<x3>), sym_name = "typed_nested_zext_same_type_shared"}> ({
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^bb0(%x : !riscv.reg<x1>):
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%zextb = "riscv.zextb"(%x) : (!riscv.reg<x1>) -> !riscv.reg<x3>
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%zextw = "riscv.zextw"(%zextb) : (!riscv.reg<x3>) -> !riscv.reg<x3>
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"func.return"(%zextb, %zextw) : (!riscv.reg<x3>, !riscv.reg<x3>) -> ()
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}) : () -> ()
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// A distinct destination register requires a retargeted zextb.
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"func.func"() <{function_type = (!riscv.reg<x1>) -> !riscv.reg<x3>, sym_name = "typed_nested_zext_distinct"}> ({
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^bb0(%x : !riscv.reg<x1>):
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%zextb = "riscv.zextb"(%x) : (!riscv.reg<x1>) -> !riscv.reg<x2>
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%zextw = "riscv.zextw"(%zextb) : (!riscv.reg<x2>) -> !riscv.reg<x3>
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"func.return"(%zextw) : (!riscv.reg<x3>) -> ()
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}) : () -> ()
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// Retargeting preserves the original operation when it has another user.
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"func.func"() <{function_type = (!riscv.reg<x1>) -> (!riscv.reg<x2>, !riscv.reg<x3>), sym_name = "typed_nested_zext_shared"}> ({
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^bb0(%x : !riscv.reg<x1>):
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%zextb = "riscv.zextb"(%x) : (!riscv.reg<x1>) -> !riscv.reg<x2>
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%zextw = "riscv.zextw"(%zextb) : (!riscv.reg<x2>) -> !riscv.reg<x3>
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"func.return"(%zextb, %zextw) : (!riscv.reg<x2>, !riscv.reg<x3>) -> ()
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}) : () -> ()
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}) : () -> ()
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// CHECK-LABEL: "sym_name" = "nested_zext"
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// CHECK: ^{{.*}}(%[[NESTED_X:.*]] : !riscv.reg):
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// CHECK-NEXT: %[[NESTED_B:.*]] = "riscv.zextb"(%[[NESTED_X]]) : (!riscv.reg) -> !riscv.reg
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// CHECK-NEXT: "func.return"(%[[NESTED_B]]) : (!riscv.reg) -> ()
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// CHECK-LABEL: "sym_name" = "typed_nested_zext"
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// CHECK: ^{{.*}}(%[[TYPED_NESTED_X:.*]] : !riscv.reg<x1>):
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// CHECK-NEXT: %[[TYPED_NESTED_B:.*]] = "riscv.zextb"(%[[TYPED_NESTED_X]]) : (!riscv.reg<x1>) -> !riscv.reg<x3>
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// CHECK-NEXT: "func.return"(%[[TYPED_NESTED_B]]) : (!riscv.reg<x3>) -> ()
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// CHECK-LABEL: "sym_name" = "typed_nested_zext_same_type_shared"
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// CHECK: ^{{.*}}(%[[TYPED_SAME_X:.*]] : !riscv.reg<x1>):
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// CHECK-NEXT: %[[TYPED_SAME_B:.*]] = "riscv.zextb"(%[[TYPED_SAME_X]]) : (!riscv.reg<x1>) -> !riscv.reg<x3>
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// CHECK-NEXT: "func.return"(%[[TYPED_SAME_B]], %[[TYPED_SAME_B]]) : (!riscv.reg<x3>, !riscv.reg<x3>) -> ()
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// CHECK-LABEL: "sym_name" = "typed_nested_zext_distinct"
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// CHECK: ^{{.*}}(%[[TYPED_DISTINCT_X:.*]] : !riscv.reg<x1>):
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// CHECK-NEXT: %[[TYPED_DISTINCT_B:.*]] = "riscv.zextb"(%[[TYPED_DISTINCT_X]]) : (!riscv.reg<x1>) -> !riscv.reg<x3>
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// CHECK-NEXT: "func.return"(%[[TYPED_DISTINCT_B]]) : (!riscv.reg<x3>) -> ()
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// CHECK-LABEL: "sym_name" = "typed_nested_zext_shared"
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// CHECK: ^{{.*}}(%[[TYPED_SHARED_X:.*]] : !riscv.reg<x1>):
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// CHECK-NEXT: %[[TYPED_SHARED_ORIGINAL:.*]] = "riscv.zextb"(%[[TYPED_SHARED_X]]) : (!riscv.reg<x1>) -> !riscv.reg<x2>
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// CHECK-NEXT: %[[TYPED_SHARED_RETARGETED:.*]] = "riscv.zextb"(%[[TYPED_SHARED_X]]) : (!riscv.reg<x1>) -> !riscv.reg<x3>
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// CHECK-NEXT: "func.return"(%[[TYPED_SHARED_ORIGINAL]], %[[TYPED_SHARED_RETARGETED]]) : (!riscv.reg<x2>, !riscv.reg<x3>) -> ()

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