xdsl-autotuning-paper-experiments/default.yaml at main · opencompl/xdsl-autotuning-paper-experiments · GitHub

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cc: clang
cc_asm: clang-unwrapped
machine: ci

xdsl-opt-backend-passes:
  avx512:
    - scf-for-loop-unroll
    - convert-vector-to-ptr
    - convert-memref-to-ptr{lower_func=true}
    - convert-ptr-type-offsets
    - canonicalize
    - convert-func-to-x86-func
    - convert-vector-to-x86{arch=avx512}
    - convert-ptr-to-x86{arch=avx512}
    - convert-arith-to-x86
    - reconcile-unrealized-casts
    - canonicalize
    - x86-infer-broadcast
    - dce
    - x86-allocate-registers{arch=avx512}
    - canonicalize

libxsmm-gemm-passes:
  - x86-prologue-epilogue-insertion

compxsmm-gemm-passes:
  avx512:
    - xsmm-apply-schedule{strategy=libxsmm-skx disable-regalloc=true}
    - x86-regalloc-verify-liveness
    - x86-allocate-registers{arch=avx512}
    - convert-x86-scf-to-x86
    - x86-prologue-epilogue-insertion

# The same schedule, except that an M tile shorter than half a vector is lowered
# to the narrowest register type that covers it instead of to a masked zmm.  The
# tiling is the one `compxsmm` gets, so a figure putting the two side by side
# prices the nano-kernel alone.
compxsmm-plusnarrow-gemm-passes:
  avx512:
    - xsmm-apply-schedule{strategy=libxsmm-skx-plusnarrow disable-regalloc=true}
    - x86-regalloc-verify-liveness
    - x86-allocate-registers{arch=avx512}
    - convert-x86-scf-to-x86
    - x86-prologue-epilogue-insertion

# The same schedule with the registers assigned by the schedule itself, the way
# libxsmm hands them out, so the figures can price our register allocator.  The
# generator has to keep its own assignment too: see `--disable-regalloc`.
compxsmm-manual-gemm-passes:
  avx512:
    - xsmm-apply-schedule{strategy=libxsmm-skx}
    - x86-regalloc-verify-liveness
    - convert-x86-scf-to-x86
    - x86-prologue-epilogue-insertion

# The pipeline template for a nano-kernel pinned instead of picked by the SKX
# heuristic. Each consumer replaces `{nanokernel}` with the strategy name.
# Registers are still xDSL's to assign, as in `compxsmm`.
compxsmm-nanokernel-passes:
  avx512:
    - xsmm-apply-schedule{strategy={nanokernel} disable-regalloc=true disable-loop-construction=true}
    - x86-regalloc-verify-liveness
    - x86-allocate-registers{arch=avx512}
    - convert-x86-scf-to-x86
    - x86-prologue-epilogue-insertion

# libxtcmm emits the linalg payload + transform-dialect schedule; this replays
# XTC's own lowering (the same passes MlirLLVMTarget runs in-process) via
# mlir-opt: apply the transform (transform-interpreter) and erase the schedule
# (symbol-privatize keeps the `matmul` entry, symbol-dce drops @__transform_main),
# then XTC's memref->llvm pipeline. Run as `mlir-opt -pass-pipeline=builtin.module(...)`.
libxtcmm-gemm-passes:
  avx512:
    - "transform-interpreter"
    - "symbol-privatize{exclude=matmul}"
    - "symbol-dce"
    - "canonicalize"
    - "cse"
    - "sccp"
    - "math-uplift-to-fma"
    - "expand-strided-metadata"
    - "convert-linalg-to-loops"
    - "lower-affine"
    - "func.func(lower-vector-mask)"
    - "convert-vector-to-scf{full-unroll=true}"
    - "scf-forall-to-parallel"
    - "convert-scf-to-openmp"
    - "canonicalize"
    - "cse"
    - "sccp"
    - "convert-scf-to-cf"
    - "canonicalize"
    - "cse"
    - "sccp"
    - "buffer-results-to-out-params"
    - "convert-func-to-llvm{use-bare-ptr-memref-call-conv=true}"
    - "finalize-memref-to-llvm"
    - "canonicalize"
    - "cse"
    - "sccp"
    - "convert-math-to-llvm"
    - "convert-vector-to-llvm{enable-x86vector=true}"
    - "convert-index-to-llvm"
    - "convert-arith-to-llvm"
    - "convert-ub-to-llvm"
    - "canonicalize"
    - "cse"
    - "sccp"
    - "convert-cf-to-llvm"
    - "convert-openmp-to-llvm"
    - "canonicalize"
    - "cse"
    - "sccp"