Annoying behaviors related to SPI GPIO mapping #19257
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Would this issue go away if you tied all unused pins to ground and configured them as outputs, set low? This information is often omitted from hardware notes, and as a (mostly) software person, I often forget to do it. The RP2 datasheet doesn't have anything explicit about requiring this. |
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There are actual differences between the different reset methods, especially with regards to external hardware (obviously) but also on chip periphials. I started on this diagram, but still need to finish it. |
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I recently spent a couple of hours debugging a mystery issue with an SPI display that turned out to be caused by some painful "gotchas" related to GPIO handling in the RP2 port:
The most problematic case here is if any extraneous SPI RX pins are left set to that function. When this occurs, the state of those pins will all be ORed together, potentially causing received data to be corrupted. (In my case, the extra pin was pulled up, so I was unable to read data at all.)
Questions:
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