conclusion.tex

Advancements toward a fully electronics-photonics monolithic node were demonstrated by improving the fundamental building block, the MOSFET, and by building of a digital electronics library. 
This library was then used with open-source tooling to produce a digital core with SPI capabilities showing that the implementation of a digital library was successful, albeit some restrictions and barriers are still in place.
First is a file we were not able to provide to the automated router is the timing library of the gates, which can either be obtained through parasitic extraction simulations or constructed via a measurement campaign
Nevertheless, not having the exact gate timing influences the maximum clock frequency of the circuit, not its logics, as the circuit will still be capable to compute at a lower speed. 
Second challenge encountered was the routing density. 
As photonic nodes are not geared toward complex and dense metallic routing (i.e. limited number of metal levels, vias do not stack, wide metals only), the automated router was not finding a solution to the maze problem when the density of the circuit was over 70\%. 
Hence, the core size is determined not only by the gate dimensions but also by the metal routing rules specified by the foundry.
To continue, the next steps of this endeavor are varied.
The supporting components in Fig.\ref{fig:Core}.A are yet to be built, in part because they are mixed or analog circuits and they need a reliable simulation environment supported by measurement of an array of sizes of $L$ and gap values.
Once done, the timing library should be generated and given to the automated router in order to complete a monolithic electronic-photonic platform in a conventional silicon photonic process. 
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