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| 1 | +/* |
| 2 | + This project is free software: you can redistribute it and/or modify |
| 3 | + it under the terms of the GNU General Public License as published by |
| 4 | + the Free Software Foundation, either version 3 of the License, or |
| 5 | + (at your option) any later version. |
| 6 | +
|
| 7 | + Multiprotocol is distributed in the hope that it will be useful, |
| 8 | + but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | + GNU General Public License for more details. |
| 11 | +
|
| 12 | + You should have received a copy of the GNU General Public License |
| 13 | + along with Multiprotocol. If not, see <http://www.gnu.org/licenses/>. |
| 14 | + |
| 15 | + Works with Traxxas 6519 receivers https://traxxas.com/sites/default/files/24CompGuide-2016.jpg . |
| 16 | + */ |
| 17 | + |
| 18 | +#if defined(TRAXXAS_CYRF6936_INO) |
| 19 | + |
| 20 | +#include "iface_cyrf6936.h" |
| 21 | + |
| 22 | +//#define TRAXXAS_FORCE_ID |
| 23 | + |
| 24 | +#define TRAXXAS_CHANNEL 0x05 |
| 25 | +#define TRAXXAS_BIND_CHANNEL 0x2B |
| 26 | +#define TRAXXAS_PACKET_SIZE 16 |
| 27 | + |
| 28 | +enum { |
| 29 | + TRAXXAS_BIND_PREP_RX=0, |
| 30 | + TRAXXAS_BIND_RX, |
| 31 | + TRAXXAS_BIND_TX1, |
| 32 | + TRAXXAS_PREP_DATA, |
| 33 | + TRAXXAS_DATA, |
| 34 | +}; |
| 35 | + |
| 36 | +const uint8_t PROGMEM TRAXXAS_sop_bind[] ={ 0x3C, 0x37, 0xCC, 0x91, 0xE2, 0xF8, 0xCC, 0x91 }; |
| 37 | +const uint8_t PROGMEM TRAXXAS_sop_data[] ={ 0xA1, 0x78, 0xDC, 0x3C, 0x9E, 0x82, 0xDC, 0x3C }; |
| 38 | +//const uint8_t PROGMEM TRAXXAS_sop_check[]={ 0x97, 0xE5, 0x14, 0x72, 0x7F, 0x1A, 0x14, 0x72 }; |
| 39 | + |
| 40 | +const uint8_t PROGMEM TRAXXAS_init_vals[][2] = { |
| 41 | + //Init from dump |
| 42 | + {CYRF_0B_PWR_CTRL, 0x00}, // PMU |
| 43 | + {CYRF_32_AUTO_CAL_TIME, 0x3C}, // Default init value |
| 44 | + {CYRF_35_AUTOCAL_OFFSET, 0x14}, // Default init value |
| 45 | + {CYRF_1B_TX_OFFSET_LSB, 0x55}, // Default init value |
| 46 | + {CYRF_1C_TX_OFFSET_MSB, 0x05}, // Default init value |
| 47 | + {CYRF_28_CLK_EN, 0x02}, // Force Receive Clock Enable |
| 48 | + {CYRF_06_RX_CFG, 0x88 | 0x02}, // AGC enabled, Fast Turn Mode enabled, adding overwrite enable to not lockup RX |
| 49 | + {CYRF_1E_RX_OVERRIDE, 0x08}, // Reject packets with 0 seed |
| 50 | + {CYRF_03_TX_CFG, 0x08 | CYRF_BIND_POWER}, // 8DR Mode, 32 chip codes |
| 51 | +}; |
| 52 | + |
| 53 | +static void __attribute__((unused)) TRAXXAS_cyrf_bind_config() |
| 54 | +{ |
| 55 | + CYRF_PROGMEM_ConfigSOPCode(TRAXXAS_sop_bind); |
| 56 | + CYRF_WriteRegister(CYRF_15_CRC_SEED_LSB, 0x5A); |
| 57 | + CYRF_WriteRegister(CYRF_16_CRC_SEED_MSB, 0x5A); |
| 58 | + CYRF_ConfigRFChannel(TRAXXAS_BIND_CHANNEL); |
| 59 | +} |
| 60 | + |
| 61 | +static void __attribute__((unused)) TRAXXAS_cyrf_data_config() |
| 62 | +{ |
| 63 | + CYRF_PROGMEM_ConfigSOPCode(TRAXXAS_sop_data); |
| 64 | + #ifdef TRAXXAS_FORCE_ID // data taken from TX dump |
| 65 | + CYRF_WriteRegister(CYRF_15_CRC_SEED_LSB, 0x1B); |
| 66 | + CYRF_WriteRegister(CYRF_16_CRC_SEED_MSB, 0x3F); |
| 67 | + #else |
| 68 | + CYRF_WriteRegister(CYRF_15_CRC_SEED_LSB, cyrfmfg_id[0]+0xB6); |
| 69 | + CYRF_WriteRegister(CYRF_16_CRC_SEED_MSB, cyrfmfg_id[1]+0x5D); |
| 70 | + #endif |
| 71 | + CYRF_ConfigRFChannel(TRAXXAS_CHANNEL); |
| 72 | + CYRF_SetTxRxMode(TX_EN); |
| 73 | +} |
| 74 | + |
| 75 | +static void __attribute__((unused)) TRAXXAS_send_data_packet() |
| 76 | +{ |
| 77 | + packet[0] = 0x01; |
| 78 | + memset(&packet[1],0x00,TRAXXAS_PACKET_SIZE-1); |
| 79 | + //Steering |
| 80 | + uint16_t ch = convert_channel_16b_nolimit(RUDDER,500,1000); |
| 81 | + packet[2]=ch>>8; |
| 82 | + packet[3]=ch; |
| 83 | + //Throttle |
| 84 | + ch = convert_channel_16b_nolimit(THROTTLE,500,1000); |
| 85 | + packet[4]=ch>>8; |
| 86 | + packet[5]=ch; |
| 87 | + //AUX3 |
| 88 | + ch = convert_channel_16b_nolimit(AILERON,500,1000); |
| 89 | + packet[6]=ch>>8; |
| 90 | + packet[7]=ch; |
| 91 | + //AUX4??? |
| 92 | + ch = convert_channel_16b_nolimit(ELEVATOR,500,1000); |
| 93 | + packet[12]=ch>>8; |
| 94 | + packet[13]=ch; |
| 95 | + |
| 96 | + CYRF_SetPower(0x08); |
| 97 | + CYRF_WriteDataPacketLen(packet, TRAXXAS_PACKET_SIZE); |
| 98 | +} |
| 99 | + |
| 100 | +uint16_t ReadTRAXXAS() |
| 101 | +{ |
| 102 | + uint8_t status; |
| 103 | + |
| 104 | + switch(phase) |
| 105 | + { |
| 106 | + case TRAXXAS_BIND_PREP_RX: |
| 107 | + TRAXXAS_cyrf_bind_config(); |
| 108 | + CYRF_SetTxRxMode(RX_EN); //Receive mode |
| 109 | + CYRF_WriteRegister(CYRF_05_RX_CTRL, 0x83); //Prepare to receive |
| 110 | + packet_count=100; //Timeout for RX |
| 111 | + phase=TRAXXAS_BIND_RX; |
| 112 | + return 700; |
| 113 | + case TRAXXAS_BIND_RX: |
| 114 | + //Read data from RX |
| 115 | + status = CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS); |
| 116 | + if((status & 0x03) == 0x02) // RXC=1, RXE=0 then 2nd check is required (debouncing) |
| 117 | + status |= CYRF_ReadRegister(CYRF_07_RX_IRQ_STATUS); |
| 118 | + debugln("s=%02X",status); |
| 119 | + CYRF_WriteRegister(CYRF_07_RX_IRQ_STATUS, 0x80); // need to set RXOW before data read |
| 120 | + if((status & 0x07) == 0x02) |
| 121 | + { // Data received with no errors |
| 122 | + len=CYRF_ReadRegister(CYRF_09_RX_COUNT); |
| 123 | + debugln("L=%02X",len) |
| 124 | + if(len==TRAXXAS_PACKET_SIZE) |
| 125 | + { |
| 126 | + CYRF_ReadDataPacketLen(packet, TRAXXAS_PACKET_SIZE); |
| 127 | + debug("RX="); |
| 128 | + for(uint8_t i=0;i<TRAXXAS_PACKET_SIZE;i++) |
| 129 | + debug(" %02X",packet[i]); |
| 130 | + debugln(""); |
| 131 | + for(uint8_t i=0;i<6;i++) |
| 132 | + packet[i+1]=cyrfmfg_id[i]; |
| 133 | + packet[10]=0x01; |
| 134 | + packet_count=12; |
| 135 | + CYRF_SetTxRxMode(TX_EN); |
| 136 | + phase=TRAXXAS_BIND_TX1; |
| 137 | + return 200; |
| 138 | + } |
| 139 | + } |
| 140 | + if( --packet_count == 0 ) |
| 141 | + { // Retry RX |
| 142 | + CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x20); // Enable RX abort |
| 143 | + CYRF_WriteRegister(CYRF_0F_XACT_CFG, 0x24); // Force end state |
| 144 | + CYRF_WriteRegister(CYRF_29_RX_ABORT, 0x00); // Disable RX abort |
| 145 | + if(--bind_counter != 0) |
| 146 | + phase=TRAXXAS_BIND_PREP_RX; // Retry receiving bind packet |
| 147 | + else |
| 148 | + phase=TRAXXAS_PREP_DATA; // Abort binding |
| 149 | + } |
| 150 | + return 700; |
| 151 | + case TRAXXAS_BIND_TX1: |
| 152 | + CYRF_WriteDataPacketLen(packet, TRAXXAS_PACKET_SIZE); |
| 153 | + debug("P="); |
| 154 | + for(uint8_t i=0;i<TRAXXAS_PACKET_SIZE;i++) |
| 155 | + debug(" %02X",packet[i]); |
| 156 | + debugln(""); |
| 157 | + if(--packet_count==0) // Switch to normal mode |
| 158 | + phase=TRAXXAS_PREP_DATA; |
| 159 | + break; |
| 160 | + case TRAXXAS_PREP_DATA: |
| 161 | + BIND_DONE; |
| 162 | + TRAXXAS_cyrf_data_config(); |
| 163 | + phase++; |
| 164 | + case TRAXXAS_DATA: |
| 165 | + TRAXXAS_send_data_packet(); |
| 166 | + break; |
| 167 | + } |
| 168 | + return 13940; |
| 169 | +} |
| 170 | + |
| 171 | +uint16_t initTRAXXAS() |
| 172 | +{ |
| 173 | + CYRF_Reset(); |
| 174 | + |
| 175 | + //Config CYRF registers |
| 176 | + for(uint8_t i = 0; i < sizeof(TRAXXAS_init_vals) / 2; i++) |
| 177 | + CYRF_WriteRegister(pgm_read_byte_near(&TRAXXAS_init_vals[i][0]), pgm_read_byte_near(&TRAXXAS_init_vals[i][1])); |
| 178 | + |
| 179 | + //Read CYRF ID |
| 180 | + CYRF_GetMfgData(cyrfmfg_id); |
| 181 | + cyrfmfg_id[0]+=RX_num; |
| 182 | + |
| 183 | + #ifdef TRAXXAS_FORCE_ID // data taken from TX dump |
| 184 | + cyrfmfg_id[0]=0x65; // CYRF MFG ID |
| 185 | + cyrfmfg_id[1]=0xE2; |
| 186 | + cyrfmfg_id[2]=0x5E; |
| 187 | + cyrfmfg_id[3]=0x55; |
| 188 | + cyrfmfg_id[4]=0x4D; |
| 189 | + cyrfmfg_id[5]=0xFE; |
| 190 | + #endif |
| 191 | + |
| 192 | + if(IS_BIND_IN_PROGRESS) |
| 193 | + { |
| 194 | + bind_counter=100; |
| 195 | + phase = TRAXXAS_BIND_PREP_RX; |
| 196 | + } |
| 197 | + else |
| 198 | + phase = TRAXXAS_PREP_DATA; |
| 199 | + return 1000; |
| 200 | +} |
| 201 | + |
| 202 | +/* |
| 203 | +Bind phase 1 |
| 204 | +CHANNEL: 0x2B |
| 205 | +SOP_CODE: 0x3C 0x37 0xCC 0x91 0xE2 0xF8 0xCC 0x91 |
| 206 | +CRC_SEED_LSB: 0x5A |
| 207 | +CRC_SEED_MSB: 0x5A |
| 208 | +RX1: 0x02 0x4A 0xA3 0x2D 0x1A 0x49 0xFE 0x06 0x00 0x00 0x02 0x01 0x06 0x06 0x00 0x00 |
| 209 | +TX1: 0x02 0x65 0xE2 0x5E 0x55 0x4D 0xFE 0xEE 0x00 0x00 0x01 0x01 0x06 0x05 0x00 0x00 |
| 210 | +Note: RX cyrfmfg_id is 0x4A,0xA3,0x2D,0x1A,0x49,0xFE and TX cyrfmfg_id is 0x65,0xE2,0x5E,0x55,0x4D,0xFE |
| 211 | +
|
| 212 | +Bind phase 2 (looks like normal mode?) |
| 213 | +CHANNEL: 0x05 |
| 214 | +SOP_CODE: 0xA1 0x78 0xDC 0x3C 0x9E 0x82 0xDC 0x3C |
| 215 | +CRC_SEED_LSB: 0x1B |
| 216 | +CRC_SEED_MSB: 0x3F |
| 217 | +RX2: 0x03 0x4A 0xA3 0x2D 0x1A 0x49 0xFE 0x06 0x00 0x00 0x02 0x01 0x06 0x06 0x00 0x00 |
| 218 | +TX2: 0x01 0x65 0x01 0xF4 0x03 0xE7 0x02 0x08 0x00 0x00 0x01 0x01 0x02 0xEE 0x00 0x00 |
| 219 | +Note: TX2 is nearly a normal packet at the exception of the 2nd byte equal to cyrfmfg_id[0] |
| 220 | +
|
| 221 | +Bind phase 3 (check?) |
| 222 | +CHANNEL: 0x22 |
| 223 | +SOP_CODE: 0x97 0xE5 0x14 0x72 0x7F 0x1A 0x14 0x72 |
| 224 | +CRC_SEED_LSB: 0xA5 |
| 225 | +CRC_SEED_MSB: 0xA5 |
| 226 | +RX3: 0x04 0x4A 0xA3 0x2D 0x1A 0x49 0xFE 0x06 0x00 0x00 0x02 0x01 0x06 0x06 0x00 0x00 |
| 227 | +
|
| 228 | +Switch to normal mode |
| 229 | +CHANNEL: 0x05 |
| 230 | +SOP_CODE: 0xA1 0x78 0xDC 0x3C 0x9E 0x82 0xDC 0x3C |
| 231 | +CRC_SEED_LSB: 0x1B |
| 232 | +CRC_SEED_MSB: 0x3F |
| 233 | +TX3: 0x01 0x00 0x02 0xA8 0x03 0xE7 0x02 0x08 0x00 0x00 0x01 0x01 0x02 0xEE 0x00 0x00 |
| 234 | +*/ |
| 235 | +#endif |
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