Unpredictable behaviour of ring counters

[skrillexxxxx]

1. When the simulation is reset globally, the counter starts from pin Q1, but it should from Q0

2. The RESET is not working properly. I tried to find a circuit where logically everything should work, but as you can see, the pulse comes to the reset input and the counter simply freezes on Q0, then mysteriously switches to Q1 without any triggers.

Counter Issue 1.txt

I know that in reality an op-amp isn’t the best for controlling a reset, so I thought perhaps this was being simulated in some way here, but unfortunately, even if I build a circuit with a Schmitt trigger, nothing changes :(

3. I’ve put together a simpler circuits here, but you can see the same problems

Counter Issue 2.txt
Counter Issue 3.txt

In general, I’ve noticed this kind of reset behaviour on other ICs. For example, a sequence generator behaves the same way. I've tried all these things above on the web/desktop versions and on my IPad - same results.

Please correct me if I’m somewhere wrong. Thank you for such a cool simulator, it’s the best!

[skrillexxxxx]

Ohh the same with the CE input ((

[skrillexxxxx]

I've found another odd thing, this time with the clock input... I just can't understand why the clock input detect something while it's 0 volts

Clock Input Issue.txt

I would really appreciate if you could explane or fix all of the above, as I simply can't get any circuit to work

[pfalstad]

There are definitely some bugs that need to be fixed relating to mixing digital and nonlinear analog components. While converging, the analog portion is generating a reset signal on the counter. The ring counter shouldn't react to this signal until convergence is finished. The solution (to issue 1, at least) is to add a delayed buffer on the Reset Out with the delay equal to the timestep.

Counter.Issue-fixed.1.txt

[pfalstad]

issue 2 and clock input issue seem to be the same, with the same fix.

I don't see any issue with 3, it seems to be working fine (because there are no analog components, everything is digital).

I think this is the same as sharpie7#864. I've been putting it off because it requires some serious rethinking/reworking of how digital chips are implemented.

[pfalstad]

I'm working on a fix for this but I think these circuits have some issues too.. If you look at circuit issue 2, just before CC4 goes high, there's a short interval where CC3 and Clk are both high (before Counter 1 has a chance to operate), which causes Trigger to be high again and Counter 2 to reset. The delay fixes that but I think it's hiding a problem that would occur in a real circuit..

[skrillexxxxx]

Legend. Many thanks for the feedback!!

[skrillexxxxx]

I had planned to use this circuit at low frequencies (musical step secuencer). I haven’t had the chance to test it yet, but in theory it should work. When the Clk signal is high, the RESET input of the second counter receives a voltage in millivolts from the cutted tail of the CC3 signal during that tiny interval you talking about. In theory, it should interpret this as a 0, and a reset should not occur

[pfalstad]

I'm not sure, it depends on the timing details of the ring counter, I guess. You might need a delayed buffer even after I release the fix for this.