Parsing declarative ISA DSL's

[attila-lendvai]

my ultimate goal is to generate an assembler for Maru to eliminate its last external dependency, and also open up the road towards a JIT.

i've looked into two candidates and did some experiments:

https://github.com/hu-dwim/hu.dwim.genassem

https://github.com/hu-dwim/hu.dwim.sleigh

i'm keeping their readme's up to date, including their status.

my current understanding is that TableGen can emit a json file that has better info than Sleigh, and is also much simpler to parse.

i'm open for any head's up if i'm walking into a forest i don't recognize, or suggestions for any better declarative descriptions for the x86 ISA.

[attila-lendvai]

so, i've made some progress. some instructions actually emit valid machine code, and there are tests that validate it using ndisasm.

i've also pushed a todo.txt with some info i've digged up.

https://github.com/hu-dwim/hu.dwim.genassem

i have some questions where you may have better insight than me (first time delving into x86, and also into assemblers)...

e.g. TableGen records 32/64 bit versions of instructions even though both emit the same machine code. e.g. bswap32r and bswap64r. their reason for this is that LLVM has a type system where this all needs to integrate.

now, does it make sense to retain this in the generated assembler? on the one hand it's pointless complexity (although, conflating them is added complexity in the generator). on the other hand, it retains some non-zero type checking (the generated instruction emitters check whether valid registers are used as args).

my plan is to map TableGen with as little modifications as possible. and then, in a second phase and probably into a different package, generate "smart" instructions that conflate e.g. all the different movs into a single emitter that dispatches on the provided args.

with this in mind, i'm leaning towards retaining the 32/64 versions as they are in TableGen, and do the DWIM stuff in the other package.

any thoughts are welcome!

[attila-lendvai]

FTR, this is how you can get a TableGen json: https://github.com/hu-dwim/hu.dwim.genassem/blob/main/bin/run-llvm-tblgen.sh