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[submodule "projects/tiny-gpu"]
path = projects/tiny-gpu
url = https://github.com/QinlinChen/tiny-gpu.git
[submodule "projects/hdmi"]
path = projects/hdmi
url = https://github.com/QinlinChen/hdmi.git
[submodule "projects/picorv32"]
path = projects/picorv32
url = https://github.com/YosysHQ/picorv32.git
[submodule "projects/darkriscv"]
path = projects/darkriscv
url = https://github.com/darklife/darkriscv.git
[submodule "projects/wujian100_open"]
path = projects/wujian100_open
url = https://github.com/XUANTIE-RV/wujian100_open.git
[submodule "projects/e203"]
path = projects/e203
url = https://github.com/riscv-mcu/e203_hbirdv2.git
[submodule "projects/32-Verilog-Mini-Projects"]
path = projects/32-Verilog-Mini-Projects
url = https://github.com/sudhamshu091/32-Verilog-Mini-Projects.git
[submodule "projects/FPGA-FOC"]
path = projects/FPGA-FOC
url = https://github.com/WangXuan95/FPGA-FOC.git
[submodule "projects/basic_verilog"]
path = projects/basic_verilog
url = https://github.com/JacyCui/basic_verilog.git
[submodule "projects/serv"]
path = projects/serv
url = https://github.com/JacyCui/serv.git
[submodule "projects/verilog-axi"]
path = projects/verilog-axi
url = https://github.com/alexforencich/verilog-axi.git
[submodule "projects/riscv"]
path = projects/riscv
url = https://github.com/ultraembedded/riscv.git
[submodule "projects/verilog-pcie"]
path = projects/verilog-pcie
url = https://github.com/alexforencich/verilog-pcie.git
[submodule "projects/miaow"]
path = projects/miaow
url = https://github.com/VerticalResearchGroup/miaow.git
[submodule "projects/biriscv"]
path = projects/biriscv
url = https://github.com/JacyCui/biriscv.git
[submodule "projects/hazard3"]
path = projects/hazard3
url = git@github.com:Wren6991/Hazard3.git
[submodule "projects/hdl"]
path = projects/hdl
url = https://github.com/QinlinChen/hdl.git
[submodule "projects/riffa"]
path = projects/riffa
url = git@github.com:KastnerRG/riffa.git
[submodule "projects/verigpu"]
path = projects/verigpu
url = git@github.com:hughperkins/VeriGPU.git
[submodule "projects/zipcpu"]
path = projects/zipcpu
url = https://github.com/ZipCPU/zipcpu.git
[submodule "projects/verilog-ethernet"]
path = projects/verilog-ethernet
url = https://github.com/alexforencich/verilog-ethernet.git
[submodule "projects/openc910"]
path = projects/openc910
url = https://github.com/XUANTIE-RV/openc910.git
[submodule "projects/scr1"]
path = projects/scr1
url = https://github.com/syntacore/scr1.git
[submodule "projects/vortex"]
path = projects/vortex
url = https://github.com/JacyCui/vortex.git