Enable NCCL broadcast path for miles

[taoluo]

Weight update in miles currently only support cpu_serialize, we need to support broadcast for distributed setting.

[zhenyulincs]

Implemented — PRs up for review:

• rlix half: feat(miles): NCCL broadcast weight-update transport (#42) #43 (transport modes, service unlock, sync-under-load hardening, plan + full evidence trail)
• miles half: feat(rlix): sender-side NCCL broadcast + topology support (rlix#42) miles#37 (sender-side NCCL in run_sync_session, atomic router re-admission, driver topology support)

How it works

Transport is now a user-selected rlix-side env, RLIX_MILES_UPDATE_TRANSPORT:

mode	behavior
cpu_serialize (default)	existing behavior — the merged change is a no-op until opt-in
auto	topology split: engines off the pipeline's train GPUs receive via NCCL broadcast (dynamic per-sync group, sender = cache_owner as rank 0); colocate engines keep cpu_serialize (NCCL cannot put the same physical GPU twice in one group)
broadcast	strict all-NCCL; fails fast at classification if any target engine is colocated with the train pool

Rank accounting is per-GPU (world_size = 1 + gpus_per_engine × n_broadcast_engines, matching SGLang's rank_offset semantics), so TP>1 engines are handled correctly.

Verified

20-rollout dual-pipeline overlap run on 4×A100 (mode auto, mem 0.8): 45 NCCL group creations (backend=nccl), 48 NCCL weight receives + 46 cpu-serialize legs (mixed transport every sync), concurrent pipeline syncs on distinct rendezvous ports, zero OOM / zero flush timeouts / clean exit. NVLink counters confirm byte-exact GiB transfers on broadcast syncs (and zero for the cpu path). Strict-mode rejection and the dedicated-train (fully-disjoint) all-NCCL topology are also exercised; details and the full design/debug trail are in plans/miles-nccl-broadcast-plan.md on #43.

Known follow-ups (documented in the plan): dual-pipeline fully-disjoint topologies need a scheduler GEN-rotation rule (deadlocks today without train pressure on shared infer GPUs); multi-node e2e; cuda_ipc for the colocate leg remains the M11.6 path.