multi clock memory

[schoeberl]

The multi-clock memory gives a warning with Chisel 5.0.2:

[deprecated] @[src/main/scala/MultiClockMemory.scala 26:21] (3 calls): The clock used to initialize the memory is different than the one used to initialize the port. If this is intentional, please pass the clock explicitly when creating the port. This behavior will be an error in 3.6.0