Interrupts/registers do not match the H7 datasheet

[yorickdewid]

The block reference manual (RM0433) lists different interrupts and registers than the current driver expects.

Found so far:

• RM044 section 56.5.16 FDCAN_IE is different than what src/interrupt.rs lists.
• RX FIFO (RXFnC.FnWM) watermark is never set which means it will default to 0. Any RAM index greater than 0 will be reported as 'overrun'.

[richardeoin]

These are differences in the STM32H7 / STM32MP1 FDCAN controller that aren't captured by the feature gates. Thanks for listing these two - have you found any more?

[yorickdewid]

So for not, but I'm sure there are more.

[richardeoin]

RM044 section 56.5.16 FDCAN_IE is different than what src/interrupt.rs lists.

Fixed by #14

RX FIFO (RXFnC.FnWM) watermark is never set which means it will default to 0

I think that should be fixed in the H7 HAL implementation, specifically here

[David-OConnor]

So fun fact should anyone come across this, but on G4 you need to reverse the interrupt lines in both the NVIC name and when enabling the line; this error goes all the way back to ST's reference manual. (Works as expected on H7)