The PAC writes EINT1 to bit 0, and EINT0 to bit 1, although the reference manual shows them the other way:
I see that was done for #4, because it is swapped on the G4. Interestingly, the same mistake is present in the G0 reference manual, but empirically, if I want to receive an interrupt on the TIM16_FDCAN_IT0 vector, I have to call can.enable_interrupt_line(fdcan::config::InterruptLine::_1, true), i.e. set EINT0, as one would expect.
I am wondering if this was a real mistake on the G4, which led to a reference manual update, which got copied onto the G0 where the mistake was fixed? I have no idea. But it seems to me that swapping these bits around is not required for G0.
The PAC writes EINT1 to bit 0, and EINT0 to bit 1, although the reference manual shows them the other way:
I see that was done for #4, because it is swapped on the G4. Interestingly, the same mistake is present in the G0 reference manual, but empirically, if I want to receive an interrupt on the
TIM16_FDCAN_IT0vector, I have to callcan.enable_interrupt_line(fdcan::config::InterruptLine::_1, true), i.e. set EINT0, as one would expect.I am wondering if this was a real mistake on the G4, which led to a reference manual update, which got copied onto the G0 where the mistake was fixed? I have no idea. But it seems to me that swapping these bits around is not required for G0.