- Have pagefault avaliable in riscv

 - Add fork spawning process in riscv
 - Add program loading function in riscv
 - Solve global pointer bug in riscv

Author: ZZJJWarth

api/ruxos_posix_api/src/imp/execve/mod.rs

@@ -3,7 +3,7 @@ mod load_elf;
 mod stack;
 
 use alloc::vec;
-use core::ffi::c_char;
+use core::{arch::asm, ffi::c_char, ptr::null};
 use ruxtask::current;
 
 use crate::{
@@ -107,11 +107,13 @@ pub fn sys_execve(pathname: *const c_char, argv: usize, envp: usize) -> ! {
 
     let mut argv = argv as *const usize;
     unsafe {
-        while *argv != 0 {
-            arg_vec.push(*argv);
-            argv = argv.add(1);
+        if argv != null() {
+            while *argv != 0 {
+                arg_vec.push(*argv);
+                argv = argv.add(1);
+            }
+            arg_vec.push(0);
         }
-        arg_vec.push(0);
     }
 
     // push
@@ -167,6 +169,17 @@ fn set_sp_and_jmp(sp: usize, entry: usize) -> ! {
         in(reg)entry,
         );
     }
+    #[cfg(target_arch = "riscv64")]
+    unsafe {
+        core::arch::asm!(
+            "
+             mv sp, {0}
+             jalr {1}
+            ",
+            in(reg) sp,
+            in(reg) entry,
+        );
+    }
     unreachable!("sys_execve: unknown arch, sp 0x{sp:x}, entry 0x{entry:x}");
 }
 

api/ruxos_posix_api/src/imp/mmap/mod.rs

@@ -9,7 +9,7 @@
 
 cfg_if::cfg_if! {
     // for X86_64 with SMP, it must flush TLB via IPI
-    if #[cfg( all(feature = "paging", any(target_arch = "aarch64", any( all(target_arch = "x86_64", feature = "irq", feature = "smp"), all(target_arch = "x86_64", not(feature = "smp")) ) ) ))] {
+    if #[cfg( all(feature = "paging", any(target_arch = "aarch64",target_arch="riscv64",any( all(target_arch = "x86_64", feature = "irq", feature = "smp"), all(target_arch = "x86_64", not(feature = "smp")) ) ) ))] {
         #[macro_use]
         mod utils;
         mod api;

api/ruxos_posix_api/src/imp/pthread/mod.rs

@@ -374,6 +374,24 @@ pub unsafe fn sys_clone(
             ruxtask::put_task(task_inner);
 
             return Ok(tid);
+        } else if (flags as u32 & ctypes::SIGCHLD) != 0 {
+            let pid = if let Some(task_ref) = ruxtask::fork_task() {
+                task_ref.id().as_u64()
+            } else {
+                let children_ref = ruxtask::current();
+                let tid = children_ref.id().as_u64();
+                let thread = Pthread {
+                    inner: children_ref.clone_as_taskref(),
+                    retval: Arc::new(Packet {
+                        result: UnsafeCell::new(core::ptr::null_mut()),
+                    }),
+                };
+                let ptr = Box::into_raw(Box::new(thread)) as *mut c_void;
+                TID_TO_PTHREAD.write().insert(tid, ForceSendSync(ptr));
+                0
+            };
+            debug!("will sys_clone <= pid: {}", pid);
+            return Ok(pid);
         } else {
             debug!("ONLY support CLONE_THREAD and SIGCHLD");
             return Err(LinuxError::EINVAL);

modules/ruxhal/src/arch/riscv/context.rs

@@ -7,9 +7,13 @@
  *   See the Mulan PSL v2 for more details.
  */
 
+use core::arch::asm;
 use core::arch::naked_asm;
+use memory_addr::PhysAddr;
 use memory_addr::VirtAddr;
 
+use super::reg_satp::RegSatp;
+
 include_asm_marcos!();
 
 /// General registers of RISC-V.
@@ -60,6 +64,7 @@ pub struct TrapFrame {
     pub sepc: usize,
     /// Supervisor Status Register.
     pub sstatus: usize,
+    pub sscratch: usize,
 }
 
 /// Saved hardware states of a task.
@@ -95,6 +100,7 @@ pub struct TaskContext {
     pub s11: usize,
 
     pub tp: usize,
+    pub gp: usize,
     // TODO: FP states
 }
 
@@ -116,21 +122,96 @@ impl TaskContext {
     ///
     /// It first saves the current task's context from CPU to this place, and then
     /// restores the next task's context from `next_ctx` to CPU.
-    pub fn switch_to(&mut self, next_ctx: &Self) {
+    pub fn switch_to(&mut self, next_ctx: &Self, page_table_addr: PhysAddr) {
         #[cfg(feature = "tls")]
         {
             self.tp = super::read_thread_pointer();
             unsafe { super::write_thread_pointer(next_ctx.tp) };
         }
+
+        let satp = RegSatp::gen_satp(riscv::register::satp::Mode::Sv39, 0, page_table_addr.into());
         unsafe {
             // TODO: switch FP states
-            context_switch(self, next_ctx)
+            context_switch(self, next_ctx, satp);
         }
     }
+
+    /// This function copy the content from src to dst,the content size is given by parameter "size"
+    /// It's only supposed to use this function for processes stack's copying
+    /// Not only the content of the src process's stack would be copied into dst's
+    /// It would also save the current context of the process to src's stack
+    ///
+    /// # Argument
+    ///  - src: The raw pointer of the src process stack
+    ///  - dst: The raw pointer of the dst process stack
+    ///  - size: The size of the stack
+    ///
+    /// # Safety
+    /// This function assumes that the parameter "size" indicate exactly the size of both stacks.
+    /// The caller must ensure this to make safe function call.
+    pub unsafe fn save_current_content(&mut self, src: *const u8, dst: *mut u8, size: usize) {
+        unsafe {
+            save_stack(src, dst, size);
+            save_current_context(self);
+        }
+    }
+}
+
+#[unsafe(naked)]
+#[allow(named_asm_labels)]
+unsafe extern "C" fn save_current_context(_current_task: &mut TaskContext) {
+    naked_asm!(
+        "
+        sd  ra,0(a0)
+        sd  sp,8(a0)
+        sd  s0,16(a0)
+        sd  s1,24(a0)
+        sd  s2,32(a0)
+        sd  s3,40(a0)
+        sd  s4,48(a0)
+        sd  s5,56(a0)
+        sd  s6,64(a0)
+        sd  s7,72(a0)
+        sd  s8,80(a0)
+        sd  s9,88(a0)
+        sd  s10,96(a0)
+        sd  s11,104(a0)
+        sd  tp,112(a0)
+        ret
+    "
+    )
+}
+
+#[unsafe(naked)]
+#[no_mangle]
+#[allow(named_asm_labels)]
+// TODO: consider using SIMD instructions to copy the stack in parallel.
+unsafe extern "C" fn save_stack(src: *const u8, dst: *mut u8, size: usize) {
+    // a0:src ; a1:dst ; a2:size
+    naked_asm!(
+        "
+        xor     a4,a4,a4
+        add    a4,a4,a2
+        start_copy:
+        ld      a5,0(a0)
+        sd      a5,0(a1)
+        addi    a0,a0,8
+        addi    a1,a1,8
+        addi    a4,a4,-8
+        bnez    a4,start_copy
+        ret
+
+        "
+    )
 }
 
 #[unsafe(naked)]
-unsafe extern "C" fn context_switch(_current_task: &mut TaskContext, _next_task: &TaskContext) {
+#[allow(named_asm_labels)]
+unsafe extern "C" fn context_switch(
+    _current_task: &mut TaskContext,
+    _next_task: &TaskContext,
+    _page_table_addr: usize,
+) {
     naked_asm!(
         "
         // save old context (callee-saved registers)
@@ -149,6 +230,12 @@ unsafe extern "C" fn context_switch(_current_task: &mut TaskContext, _next_task:
         sd     s10, 96(a0)
         sd     s11, 104(a0)
 
+        csrr    a3,satp
+        csrw    satp,a2
+        xor     a3,a3,a2
+        beqz    a3,set_satp_done
+        sfence.vma
+set_satp_done:
         // restore new context
         ld     s11, 104(a1)
         ld     s10, 96(a1)

modules/ruxhal/src/arch/riscv/mod.rs

@@ -11,8 +11,8 @@
 mod macros;
 
 mod context;
+mod reg_satp;
 mod trap;
-
 use memory_addr::{PhysAddr, VirtAddr};
 use riscv::asm;
 use riscv::register::{satp, sstatus, stvec};

modules/ruxhal/src/arch/riscv/reg_satp.rs

@@ -0,0 +1,45 @@
+use riscv::register::satp;
+
+type PhysAddr = usize;
+
+#[allow(clippy::upper_case_acronyms)]
+pub struct PPN(usize);
+
+impl From<PhysAddr> for PPN {
+    fn from(value: PhysAddr) -> Self {
+        let num = value;
+        let page_frame_num = num >> 12;
+        Self(page_frame_num)
+    }
+}
+
+impl From<PPN> for usize {
+    fn from(value: PPN) -> Self {
+        value.0
+    }
+}
+pub struct AddressSpaceID(usize);
+
+impl From<u16> for AddressSpaceID {
+    fn from(value: u16) -> Self {
+        let value = usize::from(value);
+        AddressSpaceID(value << 44)
+    }
+}
+
+impl From<AddressSpaceID> for usize {
+    fn from(value: AddressSpaceID) -> Self {
+        value.0
+    }
+}
+
+pub struct RegSatp;
+
+impl RegSatp {
+    pub fn gen_satp(mode: satp::Mode, asid: u16, page_table_addr: PhysAddr) -> usize {
+        let mode = (mode as usize) << 60;
+        let asid: AddressSpaceID = asid.into();
+        let physical_page_num: PPN = page_table_addr.into();
+        mode | usize::from(asid) | usize::from(physical_page_num)
+    }
+}

modules/ruxhal/src/arch/riscv/trap.S

@@ -1,37 +1,35 @@
 .macro SAVE_REGS, from_user
     addi    sp, sp, -{trapframe_size}
     PUSH_GENERAL_REGS
-
+    addi    t2, sp, {trapframe_size}
     csrr    t0, sepc
     csrr    t1, sstatus
-    csrrw   t2, sscratch, zero          // save sscratch (sp) and zero it
     STR     t0, sp, 31                  // tf.sepc
     STR     t1, sp, 32                  // tf.sstatus
+    STR     gp, sp, 2
     STR     t2, sp, 1                   // tf.regs.sp
-
+    csrr   gp, sscratch
 .if \from_user == 1
     LDR     t0, sp, 3                   // load supervisor tp
-    STR     gp, sp, 2                   // save user gp and tp
     STR     tp, sp, 3
     mv      tp, t0
 .endif
 .endm
 
 .macro RESTORE_REGS, from_user
+    // LDR     gp, sp, 2
 .if \from_user == 1
-    LDR     gp, sp, 2                   // load user gp and tp
     LDR     t0, sp, 3
     STR     tp, sp, 3                   // save supervisor tp
     mv      tp, t0
     addi    t0, sp, {trapframe_size}    // put supervisor sp to scratch
-    csrw    sscratch, t0
 .endif
-
+    LDR     gp, sp, 2
     LDR     t0, sp, 31
     LDR     t1, sp, 32
     csrw    sepc, t0
     csrw    sstatus, t1
-
+    //csrw    sscratch, t2
     POP_GENERAL_REGS
     LDR     sp, sp, 1                   // load sp from tf.regs.sp
 .endm
@@ -42,10 +40,9 @@
 trap_vector_base:
     // sscratch == 0: trap from S mode
     // sscratch != 0: trap from U mode
-    csrrw   sp, sscratch, sp            // switch sscratch and sp
-    bnez    sp, .Ltrap_entry_u
-
-    csrr    sp, sscratch                // put supervisor sp back
+    //csrrw   sp, sscratch, sp            // switch sscratch and sp
+    //bnez    sp, .Ltrap_entry_u
+    //csrr    sp, sscratch                // put supervisor sp back
     j       .Ltrap_entry_s
 
 .Ltrap_entry_s:

modules/ruxhal/src/arch/riscv/trap.rs

@@ -9,7 +9,7 @@
 
 use riscv::register::scause::{self, Exception as E, Trap};
 
-use super::TrapFrame;
+use super::{disable_irqs, enable_irqs, TrapFrame};
 
 include_asm_marcos!();
 
@@ -31,6 +31,8 @@ fn riscv_trap_handler(tf: &mut TrapFrame, _from_user: bool) {
         Trap::Interrupt(_) => crate::trap::handle_irq_extern(scause.bits()),
         #[cfg(feature = "musl")]
         Trap::Exception(E::UserEnvCall) => {
+            #[cfg(feature = "irq")]
+            enable_irqs();
             let ret = crate::trap::handle_syscall(
                 tf.regs.a7,
                 [
@@ -43,6 +45,23 @@ fn riscv_trap_handler(tf: &mut TrapFrame, _from_user: bool) {
                 ],
             );
             tf.regs.a0 = ret as _;
+            #[cfg(feature = "irq")]
+            disable_irqs();
+        }
+        #[cfg(feature = "paging")]
+        Trap::Exception(E::LoadPageFault) => {
+            let vaddr = riscv::register::stval::read();
+            crate::trap::handle_page_fault(vaddr, crate::trap::PageFaultCause::READ);
+        }
+        #[cfg(feature = "paging")]
+        Trap::Exception(E::StorePageFault) => {
+            let vaddr = riscv::register::stval::read();
+            crate::trap::handle_page_fault(vaddr, crate::trap::PageFaultCause::WRITE);
+        }
+        #[cfg(feature = "paging")]
+        Trap::Exception(E::InstructionPageFault) => {
+            let vaddr = riscv::register::stval::read();
+            crate::trap::handle_page_fault(vaddr, crate::trap::PageFaultCause::INSTRUCTION);
         }
         _ => {
             panic!(